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| CY7C1471BV25 | |||||
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| CY7C1473BV25, CY7C1475BV25 | |||||||
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Table 1. Pin Definitions |
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| Name | IO | Description | ||||||||||||||
| A0, A1, A | Input- | Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge | ||||||||||||||||||
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| Synchronous | of the CLK. A[1:0] are fed to the | |||||||||
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| A, |
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| B, | Input- | Byte Write Inputs, Active LOW. Qualified with |
| to conduct writes to the SRAM. Sampled | ||||||||||
| BW | BW | WE | ||||||||||||||||||
| BWC, BWD, | Synchronous | on the rising edge of CLK. | ||||||||||||||||||
| BWE, BWF, |
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| BWG, BWH |
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| Input- | Write Enable Input, Active LOW. Sampled on the rising edge of CLK if |
| is active LOW. | |||||||||
| WE | CEN | |||||||||||||||||||
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| Synchronous | This signal must be asserted LOW to initiate a write sequence. | |||||||||
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| Input- | Advance/Load Input. Used to advance the | ||||||||||
| ADV/LD | ||||||||||||||||||||
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| Synchronous | When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a | |||||||||
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| new address can be loaded into the device for an access. After being deselected, ADV/LD must | |||||||
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| be driven LOW to load a new address. | |||||||
| CLK | Input- | Clock Input. Captures all synchronous inputs to the device. CLK is qualified with |
| CLK is | ||||||||||||||||
| CEN. | ||||||||||||||||||||
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| Clock | only recognized if CEN is active LOW. | |||||||||
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| 1 |
| Input- | Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction | ||||||||||||||||
| CE | ||||||||||||||||||||
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| Synchronous | with CE2 and CE3 to select or deselect the device. | |||||||||
| CE2 | Input- | Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction | ||||||||||||||||||
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| Synchronous | with CE1 and CE3 to select or deselect the device. | |||||||||
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| 3 |
| Input- | Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction | ||||||||||||||||
| CE | ||||||||||||||||||||
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| Synchronous | with CE1 and CE2 to select or deselect the device. | |||||||||
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| Input- | Output Enable, Asynchronous Input, Active LOW. Combined with the synchronous logic | |||||||||||||||
| OE | ||||||||||||||||||||
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| Asynchronous | block inside the device to control the direction of the IO pins. When LOW, the IO pins are enabled | |||||||||
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| to behave as outputs. When deasserted HIGH, IO pins are | |||||||
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| OE is masked during the data portion of a write sequence, during the first clock when emerging | |||||||
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| from a deselected state, when the device has been deselected. | |||||||
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| Input- | Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the | |||||||||||||
| CEN | ||||||||||||||||||||
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| Synchronous | SRAM. When deasserted HIGH the clock signal is masked. Because deasserting CEN does | |||||||||
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| not deselect the device, CEN can be used to extend the previous cycle when required. | |||||||
| ZZ | Input- | ZZ “Sleep” Input. This active HIGH input places the device in a | ||||||||||||||||||
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| Asynchronous | condition with data integrity preserved. For normal operation, this pin must be LOW or left | |||||||||
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| floating. ZZ pin has an internal pull down. | |||||||
| DQs | IO- | Bidirectional Data IO Lines. As inputs, they feed into an | ||||||||||||||||||
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| Synchronous | by the rising edge of CLK. As outputs, they deliver the data contained in the memory location | |||||||||
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| specified by the addresses presented during the previous clock rise of the read cycle. The | |||||||
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| direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. | |||||||
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| When HIGH, DQs and DQPX are placed in a | |||||||
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| a deselected state, and when the device is deselected, regardless of the state of OE. | |||||||
| DQPX | IO- | Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQs. During | ||||||||||||||||||
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| Synchronous | write sequences, DQPX is controlled by BWX correspondingly. | |||||||||
| MODE | Input Strap Pin | Mode Input. Selects the Burst Order of the Device. | ||||||||||||||||||
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| When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects inter- | |||||||
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| leaved burst sequence. | |||||||
| VDD | Power Supply | Power Supply Inputs to the Core of the Device. | ||||||||||||||||||
| VDDQ | IO Power Supply | Power Supply for the IO Circuitry. | ||||||||||||||||||
| VSS | Ground | Ground for the Device. | ||||||||||||||||||
| TDO | JTAG serial output | Serial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG | ||||||||||||||||||
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| Synchronous | feature is not used, this pin must be left unconnected. This pin is not available on TQFP | |||||||||
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| packages. | |||||||
Document #: |
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| Page 8 of 30 |
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