Pin Configurations

Figure 1. 48-Pin SSOP

V CAP

 

 

1

 

48

 

 

 

VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

 

 

2

 

47

 

 

 

NC

 

 

 

 

 

A14

 

 

3

 

46

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HSB

 

 

 

 

 

 

 

A12

 

 

4

 

45

 

 

 

W

 

 

 

 

 

 

 

 

 

A7

 

 

5

 

44

 

 

 

A13

 

 

 

 

 

 

 

 

A6

 

 

6

 

43

 

 

 

 

A6

 

 

 

 

 

 

 

 

A5

 

 

7

 

42

 

 

 

 

A9

INT

 

 

8

 

41

 

 

 

NC

 

 

 

 

 

 

 

 

 

 

A4

 

 

9

 

40

 

 

 

A11

 

 

 

 

 

 

 

 

NC

 

 

10

(TOP)

39

 

 

 

NC

NC

 

 

11

38

 

 

 

NC

 

 

 

 

 

 

 

 

NC

 

 

12

 

37

 

 

 

NC

 

 

 

 

 

 

 

 

 

 

 

VSS

 

 

13

 

36

 

 

 

V SS

 

 

 

 

 

 

 

 

 

 

 

NC

 

 

14

 

35

 

 

 

NC

 

 

 

 

 

V RTCbat

 

 

15

 

34

 

 

 

V RTCcap

 

 

 

 

 

 

 

 

 

 

DQ 0

 

 

16

 

33

 

 

 

DQ 6

 

 

 

 

A3

 

 

17

 

32

 

 

 

 

G

 

 

 

 

 

 

A2

 

 

18

 

31

 

 

 

A10

 

 

 

 

 

A1

 

 

19

 

30

 

 

 

 

E

 

 

 

 

 

 

 

A0

 

 

20

 

29

 

 

 

DQ 7

 

 

 

 

 

DQ 1

 

 

21

 

28

 

 

 

DQ 5

 

 

 

 

 

DQ 2

 

 

22

 

27

 

 

 

DQ 4

 

 

 

 

 

 

X1

 

23

 

26

 

 

 

DQ 3

 

 

 

 

X2

 

24

 

25

 

 

 

V CC

 

 

 

 

STK17T88

Relative PCB Area Usage[1]

Pin Descriptions

Pin Name

IO Type

 

 

Description

A14-A0

Input

Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array or one of 16 bytes

 

 

 

 

in the clock register map.

DQ7-DQ0

I/O

Data: Bi-directional 8-bit data bus for accessing the nvSRAM and RTC.

 

 

 

Input

Chip Enable: The active low

 

input selects the device.

 

E

E

WInput Write Enable: The active low W enables data on the DQ pins to be written to the address location selected on the falling edge of E.

GInput Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high caused the DQ pins to tri-state.

 

X1

Output

Crystal Connection, drives crystal on startup.

 

X2

Input

Crystal Connection for 32.768 kHz crystal.

VRTCcap

Power Supply

Capacitor supplied backup RTC supply voltage (Left unconnected if VRTCbat is used).

VRTCbat

Power Supply

Battery supplied backup RTC supply voltage (Left unconnected if VRTCcap is used).

 

VCC

Power Supply

Power: 3.0V, +20%, -10%

 

HSB

 

I/O

Hardware Store Busy

: When low this output indicates a Store is in progress. When pulled low

 

 

 

 

external to the chip, it initiates a nonvolatile STORE operation. A weak pull up resistor keeps this

 

 

 

 

pin high if not connected. (Connection Optional).

 

INT

Output

Interrupt Control: Can be programmed to respond to the clock alarm, the watchdog timer and the

 

 

 

 

power monitor. Programmable to either active high (push/pull) or active low (open-drain)

VCAP

Power Supply

Autostore™ Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM

 

 

 

 

to nonvolatile storage elements.

 

VSS

Power Supply

Ground

 

NC

No Connect

Unlabeled pins have no internal connections.

Note

1. For detailed package size specifications, see Package Diagram on page 21.

Document Number: 001-52040 Rev. *A

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Cypress STK17T88 manual Pin Configurations, Pin Descriptions