Freescale Semiconductor DSP56366 6.5.4 Host Status Register (HSR)

HDI08 – DSP-Side Programmer’s Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
6-10 Freescale Semiconductor
for the DMA controller to supply the HA2, HA1, and HA0 signals. For 16- or 24-bit data transfers, the
DSP CPU interrupt rate is reduced by a factor of 2 or 3, respectively, from the host request rate – i.e., for
every two or three host processor data transfers of one byte each, there is only one 24-bit DSP CPU
interrupt.
If HDM1 or HDM0 are set, the HM[1:0] bits in the ICR register reflect the value of HDM[1:0].
The HDM[2:0] bits should be changed only while HEN is cleared in the HPCR.
6.5.3.6 HCR Reserved Bits 8-15
These bits are reserved. They read as zero and should be written with zero for future compatibility.
6.5.4 Host Status Register (HSR)
The HSR is a 16-bit read-only status register used by the DSP to read the status and flags of the HDI08. It
cannot be directly accessed by the host processor. The initialization values for the HSR bits are described
in Section 6.5.9, "DSP-Side Registers After Reset". The HSR bits are described in the following
paragraphs.
6.5.4.1 HSR Host Receive Data Full (HRDF) Bit 0
The HRDF bit indicates that the host receive data register (HORX) contains data from the host processor.
HRDF is set when data is transferred from the TXH:TXM:TXL registers to the HORX register. HRDF is
cleared when HORX is read by the DSP core. If HRDF is set the HDI08 generates a receive data full DMA
request, if enabled by a DSP core DMA Channel. If HRDF is set when HRIE is set, a host receive data
interrupt request is generated. HRDF can also be cleared by the host processor using the initialize function.
6.5.4.2 HSR Host Transmit Data Empty (HTDE) Bit 1
The HTDE bit indicates that the host transmit data register (HOTX) is empty and can be written by the
DSP core. HTDE is set when the HOTX register is transferred to the RXH:RXM:RXL registers. HTDE is
cleared when HOTX is written by the DSP core. If HTDE is set the HDI08 generates a transmit data empty
DMA request, if enabled by a DSP core DMA Channel. If HTDE is set when HTIE is set, a host transmit
data interrupt request is generated. HTDE can also be set by the host processor using the initialize function.
6.5.4.3 HSR Host Command Pending (HCP) Bit 2
The HCP bit indicates that the host has set the HC bit and that a host command interrupt is pending. The
HCP bit reflects the status of the HC bit in the command vector register (CVR). HC and HCP are cleared
1514131211109876543210
DMA HF1 HF0 HCP HTDE HRDF
- Reserved bit. Read as 0. Should be written with 0 for future compatibility.
Figure 6-3 Host Status Register (HSR) (X:FFFFC3)