Freescale Semiconductor DSP56366 2.2 Power, 2.3 Ground

Power
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor 2-3
2.2 Power
2.3 Ground
Table2-2 Power Inputs
Power Name Description
VCCP PLL Power — VCCP is VCC dedicated for PLL use. The voltage should be well-regulated and the input
should be provided with an extremely low impedance path to the VCC power rail. There is one VCCP
input.
VCCQL (4) Quiet Core (Low) Power — VCCQL is an isolated power for the internal processing logic. This input
must be tied externally to all other chip power inputs. The user must provide adequate external
decoupling capacitors. There are four VCCQL inputs.
VCCQH (3) Quiet External (High) Power — VCCQH is a quiet power source for I/O lines. This input must be tied
externally to all other chip power inputs. The user must provide adequate decoupling capacitors. There
are three VCCQH inputs.
VCCA (3) Address Bus Power — VCCA is an isolated power for sections of the address bus I/O drivers. This input
must be tied externally to all other chip power inputs. The user must provide adequate external
decoupling capacitors. There are three VCCA inputs.
VCCD (4) Data Bus Power — VCCD is an isolated power for sections of the data bus I/O drivers. This input must
be tied externally to all other chip power inputs. The user must provide adequate external decoupling
capacitors. There are four VCCD inputs.
VCCC (2) Bus Control Power — VCCC is an isolated power for the bus control I/O drivers. This input must be tied
externally to all other chip power inputs. The user must provide adequate external decoupling
capacitors. There are two VCCC inputs.
VCCH Host Power — VCCH is an isolated power for the HDI08 I/O drivers. This input must be tied externally
to all other chip power inputs. The user must provide adequate external decoupling capacitors. There
is one VCCH input.
VCCS (2) SHI, ESAI, ESAI_1, DAX and Timer Power — VCCS is an isolated power for the SHI, ESAI, ESAI_1,
DAX and Timer. This input must be tied externally to all other chip power inputs. The user must provide
adequate external decoupling capacitors. There are two VCCS inputs.
Table2-3 Grounds
Ground Name Description
GNDPPLL Ground — GNDP is a ground dedicated for PLL use. The connection should be provided with an
extremely low-impedance path to ground. VCCP should be bypassed to GNDP by a 0.47 µF capacitor
located as close as possible to the chip package. There is one GNDP connection.
GNDQ (4) Quiet Ground — GNDQ is an isolated ground for the internal processing logic. This connection must
be tied externally to all other chip ground connections. The user must provide adequate external
decoupling capacitors. There are four GNDQ connections.