Peripheral Overview
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor 1-9
1.5.1 Host Interface (HDI08)
The host interface (HDI08) is a byte-wide, full-duplex, double-buffered, parallel port that can be connected
directly to the data bus of a host processor. The HDI08 supports a variety of buses and provides glueless
connection with a number of industry-standard DSPs, microcomputers, microprocessors, and DMA
hardware.
The DSP core treats the HDI08 as a memory-mapped peripheral, using either standard polled or interrupt
programming techniques. Separate transmit and receive data registers are double-buffered to allow the
DSP and host processor to efficiently transfer data at high speed. Memory mapping allows DSP core
communication with the HDI08 registers to be accomplished using standard instructions and addressing
modes.
Since the host bus may operate asynchronously with the DSP core clock, the HDI08 registers are divided
into 2 banks. The “host side” bank is accessible to the external host, and the “DSP side” bank is accessible
to the DSP core.
The HDI08 supports the following three classes of interfaces:
• Host processor/MCU connection
• DMA controller
• GPIO port
Host port pins not in use may be configured as GPIO pins. The host interface provides up to 16 GPIO pins.
These pins can be programmed to function as either GPIO or host interface.
For more information on the HDI08, see Section 6, Host Interface (HDI08).
1.5.2 General Purpose Input/Output (GPIO)
The GPIO port consists of as many as 37 programmable signals, all of which are also used by the
peripherals (HDI08, ESAI, ESAI_1, DAX, and TEC). There are no dedicated GPIO signals. The signals
are configured as GPIO after hardware reset. Register programming techniques for all GPIO functionality
among these interfaces are very similar.
1.5.3 Triple Timer (TEC)
This section describes a peripheral module composed of a common 21-bit prescaler and three independent
and identical general purpose 24-bit timer/event counters, each one having its own register set.
Each timer can use internal or external clocking and can interrupt the DSP after a specified number of
events (clocks). Timer 0 can signal an external device after counting internal events. Each timer can also
be used to trigger DMA transfers after a specified number of events (clocks) occurred. One timer (Timer
0) connects to the external world through one bidirectional pin TIO0. When TIO0 is configured as input,
the timer functions as an external event counter or can measure external pulse width/signal period. When
TIO0 is used as output the timer is functioning as either a timer, a watchdog or a Pulse Width Modulator.
When the TIO0 pin is not used by the timer it can be used as a General Purpose Input/Output Pin. Refer
to Section 11, "Timer/ Event Counter".