Freescale Semiconductor DSP56366 6.5.1 Host Receive Data Register (HORX), 6.5.2 Host Transmit Data Register (HOTX)

HDI08 – DSP-Side Programmer’s Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
6-6 Freescale Semiconductor
The eight host processor registers consists of two data registers and six control registers. All registers can
be accessed by the DSP core but not by the external processor.
Data registers are 24-bit registers used for high-speed data transfer to and from the DSP. They are as
follows:
• Host Data Receive Register (HORX)
• Host Data Transmit Register (HOTX)
The control registers are 16-bit registers used to control the HDI08 functions. The eight MSBs in the
control registers are read by the DSP as zero. The control registers are as follows:
• Host control register (HCR)
• Host status register (HSR)
• Host base address register (HBAR)
• Host port control register (HPCR)
• Host GPIO data direction register (HDDR)
• Host GPIO data register (HDR)
Hardware and software reset disable the HDI08. After reset, the HDI08 signals are configured as GPIO
with all pins disconnected.
6.5.1 Host Receive Data Register (HORX)
The 24-bit read-only HORX register is used for host-to-DSP data transfers. The HORX register is loaded
with 24-bit data from the transmit data registers (TXH:TXM:TXL) on the host side when both the transmit
data register empty TXDE (host side) and host receive data full HRDF (DSP side) bits are cleared. This
transfer operation sets both the TXDE and HRDF flags. The HORX register contains valid data when the
HRDF bit is set. Reading HORX clears HRDF. The DSP may program the HRIE bit to cause a host receive
data interrupt when HRDF is set. Also, a DMA channel may be programmed to read the HORX when
HRDF is set.
6.5.2 Host Transmit Data Register (HOTX)
The 24-bit write-only HOTX register is used for DSP- to-host data transfers. Writing to the HOTX register
clears the host transfer data empty flag HTDE (DSP side). The contents of the HOTX register are
transferred as 24-bit data to the receive byte registers (RXH:RXM:RXL) when both the HTDE flag (DSP
side) and receive data full RXDF flag (host side) are cleared. This transfer operation sets the RXDF and
HTDE flags. The DSP may set the HTIE bit to cause a host transmit data interrupt when HTDE is set. Also,
a DMA Channel may be programmed to write to HOTX when HTDE is set. To prevent the previous data
from being overwritten, data should not be written to the HOTX until the HTDE flag is set.