Freescale Semiconductor DSP56366 1.3 DSP56366 Audio Processor Architecture, 1.4 DSP56300 Core Functional Blocks

DSP56366 Audio Processor Architecture
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor 1-3
— Off-chip expansion up to two 16M × 24-bit word of Data memory.
— Off-chip expansion up to 16M × 24-bit word of Program memory.
— Simultaneous glueless interface to SRAM and DRAM.
• Peripheral modules
— Serial Audio Interface (ESAI): up to 4 receivers and up to 6 transmitters, master or slave. I2S,
Sony, AC97, network and other programmable protocols.
— Serial Audio Interface I (ESAI_1): up to 4 receivers and up to 6 transmitters, master or slave.
I2S, Sony, AC97, network and other programmable protocols
The ESAI_1 shares four of the data pins with ESAI, and ESAI_1 does NOT support HCKR and
HCKT (high frequency clocks)
— Serial Host Interface (SHI): SPI and I2C protocols, multi master capability, 10-word receive
FIFO, support for 8, 16 and 24-bit words.
— Byte-wide parallel Host Interface (HDI08) with DMA support.
— Triple Timer module (TEC).
— Digital Audio Transmitter (DAX): 1 serial transmitter capable of supporting the SPDIF,
IEC958, CP-340 and AES/EBU digital audio formats.
— Pins of unused peripherals (except SHI) may be programmed as GPIO lines.
• 144-pin plastic TQFP package.
1.3 DSP56366 Audio Processor Architecture
This section defines the DSP56366 audio processor architecture. The audio processor is composed of the
following units:
• The DSP56300 core is composed of the Data ALU, Address Generation Unit, Program Controller,
Instruction-Cache Controller, DMA Controller, PLL-based clock oscillator, Memory Module
Interface, Peripheral Module Interface and the On-Chip Emulator (OnCE). The DSP56300 core is
described in the document DSP56300 24-Bit Digital Signal Processor Family Manual, Freescale
publication DSP56300FM.
• Memory modules.
• Peripheral modules. The peripheral modules are defined in the following sections.
Memory sizes in the block diagram are defaults. Memory may be differently partitioned, according to the
memory mode of the chip. See Section 1.4.8, "On-Chip Memory" for more details about memory size.
1.4 DSP56300 Core Functional Blocks
The DSP56300 core provides the following functional blocks:
• Data arithmetic logic unit (Data ALU)
• Address generation unit (AGU)
• Program control unit (PCU)
• Bus interface unit (BIU)
• DMA controller (with six channels)