Freescale Semiconductor DSP56366 9.3.2.1 TCCR_1 Tx High Freq. Clock Divider (TFP3-TFP0) - Bits 1417, 9.3.2.2 TCCR_1 Tx High Freq. Clock Polarity (THCKP) - Bit 20, 9.3.2.3 TCCR_1 Tx High Freq. Clock Direction (THCKD) - Bit 23

ESAI_1 Programming Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
9-6 Freescale Semiconductor
9.3.2.1 TCCR_1 Tx High Freq. Clock Divider (TFP3-TFP0) - Bits 14–17
Since the ESAI_1 does not have the transmitter high frequency clock pin, the TFP3–TFP0 bits simply
specify an additional division ratio in the clock divider chain. See Figure 9-4.
9.3.2.2 TCCR_1 Tx High Freq. Clock Polarity (THCKP) - Bit 20
The ESAI_1 does not have the transmitter high frequency clock pin. It it recommended that THCKP
should be kept cleared.
9.3.2.3 TCCR_1 Tx High Freq. Clock Direction (THCKD) - Bit 23
The ESAI_1 does not have the transmitter high frequency clock pin. THCKD must be set for proper
ESAI_1 transmitter section operation.
11109876543210
Y:$FFFF96 TDC2 TDC1 TDC0 TPSR TPM7 TPM6 TPM5 TPM4 TPM3 TPM2 TPM1 TPM0
23 22 21 20 19 18 17 16 15 14 13 12
THCKD TFSD TCKD THCKP TFSP TCKP TFP3 TFP2 TFP1 TFP0 TDC4 TDC3
Figure 9-3 TCCR_1 Register
Table9-2 Transmitter Clock Sources
THCKD TFSD TCKD
Transmitter
Bit Clock
Source
OUTPUTS
0 X X Reserved
100SCKT_1
1 0 1 INT SCKT_1
110SCKT_1FST_1
1 1 1 I NT FST_1 SCKT_1