Freescale Semiconductor DSP56366 2.6 Interrupt and Mode Control

Interrupt and Mode Control
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor 2-7
2.6 Interrupt and Mode Control
The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset.
After RESET is deasserted, these inputs are hardware interrupt request lines.
BG Input Ignored Input Bus Grant — BG is an active-low input. BG is asserted by an external bus
arbitration circuit when the DSP56364 becomes the next bus master. When
BG is asserted, the DSP56364 must wait until BB is deasserted before taking
bus mastership. When BG is deasserted, bus mastership is typically given up
at the end of the current bus cycle. This may occur in the middle of an
instruction that requires more than one external bus cycle for execution.
For proper BG operation, the asynchronous bus arbitration enable bit (ABE)
in the OMR register must be set.
BB Input/
Output
Input Bus Busy — BB is a bidirectional active-low input/output. BB indicates that
the bus is active. Only after BB is deasserted can the pending bus master
become the bus master (and then assert the signal again). The bus master
may keep BB asserted after ceasing bus activity regardless of whether BR is
asserted or deasserted. This is called “bus parking” and allows the current
bus master to reuse the bus without rearbitration until another device requires
the bus. The deassertion of BB is done by an “active pull-up” method (i.e., BB
is driven high and then released and held high by an external pull-up resistor).
For proper BB operation, the asynchronous bus arbitration enable bit (ABE)
in the OMR register must be set.
BB requires an external pull-up resistor.
Table2-7 External Bus Control Signals (continued)
Signal Name Type State during
Reset Signal Description