Freescale Semiconductor DSP56366 8.3.5 ESAI Common Control Register (SAICR)

ESAI Programming Model

DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4

Freescale Semiconductor 8-31

When REIE is set, the DSP is interrupted when both RDF and ROE in the SAISR status register are set.

When REIE is cleared, this interrupt is disabled. Reading the SAISR status register followed by reading

the enabled receivers data registers clears ROE, thus clearing the pending interrupt.

The REDIE control bit is used to enable the receive even slot data interrupts. If REDIE is set, the receive

even slot data interrupts are enabled. If REDIE is cleared, the receive even slot data interrupts are disabled.

A receive even slot data interrupt request is generated if REDIE is set and the REDF status flag in the

SAISR status register is set. Even time slots are all even-numbered time slots (0, 2, 4, etc.) when operating

in network mode. The zero time slot is marked by the frame sync signal and is considered to be even.

Reading all the data registers of the enabled receivers clears the REDF flag, thus servicing the interrupt.

Receive interrupts with exception have higher priority than receive even slot data interrupts, therefore if

exception occurs (ROE is set) and REIE is set, the ESAI requests an ESAI receive data with exception

interrupt from the interrupt controller.

The DSP is interrupted when RIE and the RDF flag in the SAISR status register are set. When RIE is

cleared, this interrupt is disabled. Reading the receive data registers of the enabled receivers clears RDF,

thus clearing the interrupt.

Receive interrupts with exception have higher priority than normal receive data interrupts, therefore if

exception occurs (ROE is set) and REIE is set, the ESAI requests an ESAI receive data with exception

interrupt from the interrupt controller.

RLIE enables an interrupt after the last slot of a frame ended in network mode only. When RLIE is set the

DSP is interrupted after the last slot in a frame ended regardless of the receive mask register setting. When

RLIE is cleared the receive last slot interrupt is disabled. Hardware and software reset clear RLIE. RLIE

is disabled when RDC[4:0]=00000 (on-demand mode). The use of the receive last slot interrupt is

described in Section 8.4.3, "ESAI Interrupt Requests".

8.3.5 ESAI Common Control Register (SAICR)

The read/write Common Control Register (SAICR) contains control bits for functions that affect both the

receive and transmit sections of the ESAI.See Figure 8-10.