Freescale Semiconductor DSP56366 10.7 GPIO (PORT D) - Pins and Registers

GPIO (PORT D) - Pins and Registers
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
10-12 Freescale Semiconductor
Figure 10-6 Examples of data organization in memory
10.6.5 DAX Operation During Stop
The DAX operation cannot continue when the DSP is in the stop state since no DSP clocks are active.
While the DSP is in the stop state, the DAX will remain in the individual reset state and the status flags
are initialized as described for resets. No DAX control bits are affected. The DAX should be disabled
before the DSP enters the stop state.
10.7 GPIO (PORT D) - Pins and Registers
The Port D GPIO functionality of the DAX is controlled by three registers: Port D Control Register
(PCRD), Port D Direction Register (PRRD) and Port D Data Register (PDRD).
10.7.1 Port D Control Register (PCRD)
The read/write 24-bit DAX Port D Control Register controls the functionality of the DAX GPIO pins. Each
of the PC[1:0] bits controls the functionality of the corresponding port pin. When a PC[i] bit is set, the
corresponding port pin is configured as a DAX pin. When a PC[i] bit is cleared, the corresponding port pin
is configured as GPIO pin. If both PC1 and PC0 are cleared, the DAX is disabled. Hardware and software
reset clear all PCRD bits.
Non-Audio Data
Channel A
Channel A
Channel B
Channel B
Non-Audio Data
Non-Audio Data
Non-Audio Data
Channel A
Channel A
Channel B
Channel B
$000000
$00000B
$000005
$000004
$000003
$000002
$000001
$000007
$000006
$00000A
$00009
$000008
Non-audio data bits change from
frame to frame
$000000
$00000B
$000005
$000004
$000003
$000002
$000001
$000007
$000006
$00000A
$000009
$000008
Non-audio data bits do not
change from frame to frame
Channel A
Channel A
Channel A
Channel A
Channel A
Channel A
Channel B
Channel B
Channel B
Channel B
Channel B
Channel B