Freescale Semiconductor DSP56366 user manual PLL

Programming Sheets
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
D-20 Freescale Semiconductor
Figure D-5. Phase Lock Loop Control Register (PCTL)
Application: Date:
Programmer:
Sheet 5 of 5
PLL
1514131211109876543210
MF7 MF5 MF4 MF3 MF2 MF1 MF0
19 18 17 1623 22 21 20
PENCODPD1PD3 MF6PD2 XTLD XTLR DF2 DF1 DF0 MF11PD0 PSTP MF10 MF9 MF8
PLL Control
Register (PCTL)
X:$FFFFFD Read/Write
Reset = $010005
XTAL Disable Bit (XTLD) 0 = Enable Xtal Oscillator 1 = EXTAL Driven From
An External Source
Clock Output Disable (COD)
0 = 50% Duty Cycle Clock
1 = Pin Held In High State
Crystal Range Bit (XTLR)
0 = External Xtal Freq >200KHz
1 = External Xtal Freq <200KHz
Predivision Factor Bits (PD0 – PD3)
PD3 – PD0 Predivision Factor PDF
$0 $1 $2
• • •
$F
1 2 3
• • •
16
Multiplication Factor Bits MF0 – MF11
MF11 – MF0 Multiplication Factor MF
$000 $001 $002
• • •
$FFE
$FFF
1 2 3
• • •
4095 4096
Division Factor Bits (DF0 – DF2)
DF2 – DF0 Division Factor DF
$0 $1 $2
• • •
$7
20
21 22
• • •
27
PSTP and PEN Relationship
PSTP PEN Operation During STOP Recovery Time
for STOP
Power Consumption
during STOP
PLL Oscillator
0 x Disabled Disabled Long Minimal 1 0 Disabled Enabled Short Lower 1 1 Enabled Enabled Short Higher
Note that bits XTLR, COD
and XTLD have no effect
on DSP56366 operation