5.5 Ultra DMA Feature Set

13)The host shall neither negate STOP nor HSTROBE until at least tACK after negating DMACK-.

14)The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least tACK after negating DMACK.

5.5.5Ultra DMA CRC rules

The following is a list of rules for calculating CRC, determining if a CRC error has occurred during an Ultra DMA burst, and reporting any error that occurs at the end of a command.

a)Both the host and the device shall have a 16-bit CRC calculation function.

b)Both the host and the device shall calculate a CRC value for each Ultra DMA burst.

c)The CRC function in the host and the device shall be initialized with a seed of 4ABAh at the beginning of an Ultra DMA burst before any data is transferred.

d)For each STROBE transition used for data transfer, both the host and the device shall calculate a new CRC value by applying the CRC polynomial to the current value of their individual CRC functions and the word being transferred. CRC is not calculated for the return of STROBE to the asserted state after the Ultra DMA burst termination request has been acknowledged.

e)At the end of any Ultra DMA burst the host shall send the results of its CRC calculation function to the device on DD (15:0) with the negation of DMACK-.

f)The device shall then compare the CRC data from the host with the calculated value in its own CRC calculation function. If the two values do not match, the device shall save the error and report it at the end of the command. A subsequent Ultra DMA burst for the same command that does not have a CRC error shall not clear an error saved from a previous Ultra DMa burst in the same command. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred.

g)For READ DMA or WRITE DMA commands: When a CRC error is detected, it shall be reported by setting both ICRC and ABRT (bit 7 and bit 2 in the Error register) to one. ICRC is defined as the "Interface CRC Error" bit. The host shall respond to this error by re-issuing the command.

h)A host may send extra data words on the last Ultra DMA burst of a data out command. If a device determines that all data has been transferred for a command, the device shall terminate the burst. A device may have already received more data words than were required for the command. These extra words are used by both the host and the device to calculate the CRC, but, on an Ultra DMA data out burst, the extra words shall be discarded by the device.

C141-E258

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Fujitsu MHW2040AC, MHW2060AC manual Ultra DMA CRC rules
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MHW2060AC, MHW2040AC specifications

The Fujitsu MHW2040AC and MHW2060AC are notable hard disk drives (HDDs) that have been widely used in various computing applications, especially in laptops and compact devices. These models are part of Fujitsu's commitment to providing reliable storage solutions that meet the demands of modern computing.

The MHW2040AC offers a storage capacity of 40 GB, while the MHW2060AC provides a slightly larger capacity at 60 GB. This range of storage makes both models suitable for users looking for dependable space for documents, multimedia files, and software applications. Both drives utilize a 2.5-inch form factor, ideal for mobile computing, as they are lightweight and designed to fit into space-constrained environments.

In terms of performance, both drives operate at a spindle speed of 5400 RPM. This speed strikes a balance between power consumption and performance, making these drives an efficient choice for everyday tasks, such as web browsing and office applications. The drives are equipped with an interface of Ultra ATA/133, which enables faster data transfer rates compared to older models, thereby enhancing overall system responsiveness.

The MHW2040AC and MHW2060AC also incorporate several advanced technologies to bolster their performance and reliability. One such feature is the use of a fluid dynamic bearing (FDB) for the spindle motor, which minimizes noise and vibration, thus improving the overall user experience. Additionally, both drives come with error correction technology that helps maintain data integrity by detecting and correcting errors during read and write operations.

Moreover, these HDDs feature a shock sensor that can detect sudden movements, allowing the drive to park its heads to prevent data loss and hardware damage. This is particularly beneficial in mobile environments where the risks of impact are higher.

Both the MHW2040AC and MHW2060AC are designed with energy-saving features, making them an environmentally responsible choice for energy-conscious consumers. Their low power consumption not only contributes to a reduced carbon footprint but also extends battery life for portable devices.

In summary, the Fujitsu MHW2040AC and MHW2060AC are reliable, efficient, and user-friendly hard disk drives that combine moderate capacities with advanced features designed to enhance performance, ensure data integrity, and extend device longevity. These drives are well-suited for a range of applications, making them a solid choice for users seeking dependable storage solutions.
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