Fujitsu MHW2060AC, MHW2040AC manual Normal DMA data transfer

Models: MHW2060AC MHW2040AC

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Interface

f)When the command execution is completed, the device clears both BSY and DRQ bits and asserts the INTRQ signal. Then, the host reads the Status register.

g)The host resets the DMA channel.

Figure 5.7 shows the correct DMA data transfer protocol.

f

g

d

d

f e

Figure 5.7 Normal DMA data transfer

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Fujitsu MHW2060AC, MHW2040AC manual Normal DMA data transfer