Interrupts

The following table suggests a logical interrupt mapping of interrupt sources. It reflects a typical configuration, but you can change these interrupts. Use the information to determine how to program each interrupt. The actual interrupt map is defined using configuration registers in the I/O controller. I/O Redirection Registers in the I/O APIC are provided for each interrupt signal. The signals define hardware interrupt signal characteristics for APIC messages sent to local APIC(s).

Important If you disable either IDE controller to free the interrupt for that controller, you must physically unplug the IDE cable from the system board. Simply disabling the drive by configuring the SSU option does not make the interrupt available.

InterruptI/O APIC

Description

 

Level

 

 

 

 

INTR

INT0

Processor interrupt

 

 

 

NMI

N/A

NMI from PIC to processor

 

 

 

IRQ1

INT1

Keyboard interrupt

 

 

 

Cascade

INT2

Interrupt signal from second 8259

 

 

 

IRQ3

INT3

Serial port A or B interrupt from SIO device (you can

 

 

configure either)

 

 

 

IRQ4

INT4

Serial port A or B interrupt from SIO device (you can

 

 

configure either)

 

 

 

IRQ5

INT5

Parallel port II

 

 

 

IRQ6

INT6

Diskette port

 

 

 

IRQ7

INT7

Parallel port

 

 

 

IRQ8_L

INT8

RTC interrupt

 

 

 

IRQ9

INT9

Signal control interrupt (SCI) used by

 

 

ACPI-compliant operating system

 

 

 

130Reference Data