IBM Z10 BC manual z10 BC Design and Technology

z10 BC Design and Technology

The System z10 BC is designed to provide balanced system performance. From processor storage to the system’s I/O and network channels, end-to-end bandwidth is provided and designed to deliver data where and when it is needed.

The processor subsystem is comprised of one CPC, which houses the processor units (PUs), Storage Controllers (SCs), memory, Self-Time-Interconnects (STI)/Infi niBand (IFB) and Oscillator/External Time Reference (ETR). The z10 BC design provides growth paths up to a 10 engine system where each of the 10 PUs has full access to all system resources, specifi cally memory and I/O.

The z10 BC uses the same processor chip as the z10 EC, relying only on 3 out of 4 functional cores per chip. Each chip is individually packaged in an SCM. Four SCMs will be plugged in the processor board providing the 12 PUs for the design. Clock frequency will be 3.5 GHz.

There are three active cores per PU, an L1 cache divided into a 64 KB cache for instructions and a 128 KB cache for data. Each PU also has an L1.5 cache. This cache is 3 MB in size. Each L1 cache has a Translation Look-aside Buffer (TLB) of 512 entries associated with it. The PU, which uses a high-frequency z/Architecture microprocessor core, is built on CMOS 11S chip technology and has a cycle time of approximately 0.286 nanoseconds.

The PU chip includes data compression and crypto- graphic functions. Hardware data compression can play a signifi cant role in improving performance and saving costs over doing compression in software. Standard clear key cryptographic processors right on the processor translate to high-speed cryptography for protecting data in storage, integrated as part of the PU.

Speed and precision in numerical computing are important for all our customers. The z10 BC offers improvements for decimal fl oating point instructions, because each z10 processor chip has its own hardware decimal fl oating point unit, designed to improve performance over that provided by the System z9. Decimal calculations are often used in fi nancial applications and those done using other

floating point facilities have typically been performed by software through the use of libraries. With a hardware decimal fl oating point unit some of these calculations may be done directly and accelerated.

The design of the z10 BC provides the fl exibility to con-

figure the PUs for different uses; There are 12 PUs per system, two are designated as System Assist Processors (SAPs) standard per system. The remaining 10 PUs are available to be characterized as either CPs, ICF proces- sors for Coupling Facility applications, or IFLs for Linux applications and z/VM hosting Linux as a guest, System z10 Application Assist Processors (zAAPs), System z10 Integrated Information Processors (zIIPs) or as optional SAPs and provide you with tremendous fl exibility in estab- lishing the best system for running applications.

The z10 BC can support from the 4 GB minimum memory up to 248 GB of available real memory per server for grow- ing application needs. A new 8 GB fi xed HSA which is managed separately from customer memory. This fi xed HSA is designed to improve availability by avoiding out- ages that were necessary on prior models to increase its size. There are up to 12 I/O interconnects per system at 6 GBps each.

The z10 BC supports a combination of Memory Bus Adapter (MBA) and Host Channel Adapter (HCA) fanout cards. New MBA fanout cards are used exclusively for ICB-4. New ICB-4 cables are needed for z10 BC. The Infi niBand Multiplexer (IFB-MP) card replaces the Self-

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