Modem Control Register MCR, Line Control Register LCR

Parallel Host Interface 16C450/16C550A UART

9.2.4Modem Control Register (MCR)

Figure 17. Modem Control Register (MCR)

Loop

Out 2

Out 1

RTS

DTR

		This register controls the DTE-DCE UART interface.

	Bit 7:5	Not used—These bits are permanently set to ‘0’.

		Loop Bit—When set to ‘1’, this bit configures the UART for loopback diagnostic testing. In diagnostic mode,
		any data that is written to the THR (Transmit Holding register) is looped back to the RBR (Receiver Buffer
		register).
	Bit 4	After writing a data byte to the THR register in loopback mode, the DTE must read the RBR register before
		writing a new data byte to the THR.
		Unlike a real 16C450 UART, the modem signals OUT1, OUT2, RTS, and DTR are not looped back to the
		MSR register.

	Bit 3	Out 2—This bit, when set to ‘1’ by the DTE, enables the HINT output pin. When set to ‘0’, this bit causes the
	Bit 3	HINT pin to be in a high-impedance state.
		HINT pin to be in a high-impedance state.

	Bit 2	Out 1—This read/write bit is not used for any specific functions.

	Bit 1	RTS (Request to Send)—This bit when set to ‘1’, indicates that the DTE is ready to send data to the modem.

	Bit 0	DTR (Data Terminal Ready)—When set to ‘1’, this bit indicates that the DTE is read to establish a
	Bit 0	communication link.
		communication link.

9.2.5Line Control Register (LCR)

Figure 18. Line Control Register (LCR)

DLAB

SBRK

SPAR

EPS

PEN

STB

WLS1

WLS0

This register specifies the asynchronous data communication exchange format. The modem supports up to 10-bit data characters (1 start bit + # of data character bits + parity + # of stop bits).

		Divisor Latch Access Bit (DLAB)—This bit must be set to ‘1’ to access the divisor latches of the baud rate
	Bit 7	generator during a read or write operation. The UART registers 1 and 0 are used for the divisor latches. This
	Bit 7	bit must be set to ‘0’ to access the Receiver Buffer register (RBR), the THR (Transmitter Holding register) or

		the IER (Interrupt Enable register).

		SBRK (Set Break)—This bit is used to send a long-space disconnect message to the remote modem.
		The procedure is as follows:

•After the THRE bit has been set to ‘1’ by the DCE and before setting the SBRK bit, the DTE needs to write

Bit 6

a NULL ($00h) character to the THR.

•The DTE then sets the SBRK bit after the next time the THRE bit is set by the DCE (a long space is now being transmitted).

•To return to normal transmission mode, wait for the TEMT to be equal to ‘1’, then reset the SBRK bit.

		SPAR (Stick Parity)—When this bit is set to ‘1’, stick parity is enabled. When configured for stick parity (SPAR
	Bit 5	= 1), even parity (EPS = 1) with parity enable (PEN = 1), then the parity bit is transmitted and checked as a
	Bit 5	logic ‘0’. When configured for stick parity (SPAR = 1), odd parity (EPS = 0) and parity enable (PEN = 1) are set

		to ‘1’, then the parity bit is transmitted and checked as a logic ‘1’.

536EX Chipset Developer’s Manual

Intel Confidential

537EX specifications

The Intel 537EX is a powerful and innovative embedded processor designed for a range of applications, particularly in the fields of industrial automation, telecommunications, and transport management systems. This processor is a member of Intel's embedded product line, tailored specifically to meet the demands of systems that require high reliability and long lifecycle support.

One of the main features of the Intel 537EX is its multi-core architecture, which enables efficient parallel processing capabilities. This allows for the execution of multiple tasks simultaneously, significantly improving overall system performance. The processor also incorporates Intel’s advanced power management technology, which ensures that the device consumes energy efficiently, enhances thermal performance, and prolongs the lifespan of the system.

The Intel 537EX supports a range of connectivity options, including high-speed Ethernet and Serial ATA interfaces. This ensures that it can easily integrate into existing systems, seamlessly supporting applications that require robust data transfer capabilities. Additionally, the processor is equipped with multiple I/O ports, facilitating the connection of various peripherals and sensors, which is crucial in industrial applications.

One of the standout technologies within the Intel 537EX is its support for hardware virtualization. This feature allows for the creation of multiple virtual environments within a single physical structure, optimizing resource utilization and enhancing system flexibility. Additionally, Intel’s integrated security technologies provide a significant layer of protection against potential threats, ensuring that embedded systems remain secure.

Another characteristic of the Intel 537EX is its extensive software support, which includes compatibility with various operating systems and development environments. This versatility makes it an attractive choice for developers looking to build or upgrade their embedded systems. With access to Intel's comprehensive software tools, developers can quickly optimize applications to take full advantage of the processor's capabilities.

The Intel 537EX also boasts excellent thermal performance, allowing it to operate efficiently in harsh environments. This is crucial for embedded applications in industrial settings where temperature fluctuations are common. Overall, the Intel 537EX is engineered to deliver high-performance processing power, superior connectivity, and enhanced security, solidifying its position as a reliable choice for demanding embedded applications.

Intel 537EX Modem Control Register MCR, Line Control Register LCR, IER Interrupt Enable register

Models: 537EX