Datasheet 43
Signal Descriptions
6Signal Descriptions
This chapter describes the processor signals. The signals are arranged in functional
groups according to their associated interface or category.
6.1 System Memory Interface Signals
Table 6-1. Memory Channel DDR0, DDR1, DDR2, DDR3
Signal Name Description
DDR{0/1/2/3}_BA[2:0] Bank Address: These signals define the bank which is the destination for
the current Activate, Read, Write, or PRECHARGE command.
DDR{0/1/2/3}_CAS_N Column Address Strobe
DDR{0/1/2/3}_CKE[5:0] Clock Enable
DDR{0/1/2/3}_CLK_DN[3:0]
DDR{0/1/2/3}_CLK_DP[3:0]
Differential Clocks to the DIMM: All command and control signals are
valid on the rising edge of clock.
DDR{0/1/2/3}_CS_N[9:0] Chip Select: Each signal selects one rank as the target of the command
and address.
DDR{0/1/2/3}_DQ[63:00] Data Bus: DDR3 Data bits.
DDR{0/1/2/3}_DQS_DP[17:00]
DDR{0/1/2/3}_DQS_DN[17:00]
Data strobe: This is a differential pair Data Strobe. Differential strobes
latch data for each DRAM. Different numbers of strobes are used
depending on whether the connected DRAMs are x4,x8. Driven with edges
in center of data, receive edges are aligned with data edges.
DDR{0/1/2/3}_MA[15:00]
Memory Address: Selects the Row address for Reads and writes, and the
column address for activates. Also used to set values for DRAM
configuration registers.
DDR{0/1/2/3}_ODT[5:0] On-Die Termination: Enables DRAM on die termination during Data
Write or Data Read transactions.
DDR{0/1/2/3}_RAS_N Row Address Strobe
DDR{0/1/2/3}_WE_N Write Enable