Electrical Specifications
68 Datasheet
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The voltage rail VCCD which will be set to 1.50V or 1.35V nominal depending on the voltage of all DIMMs connected to the
processor.
3. VIL is the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
4. VIH is the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
5. VIH and VOH may experience excursions above VCCD. However, input signal drivers must comply with the signal quality
specifications.
6. This is the pull down driver resistance. Reset drive does not have a termination.
7. RVTT_TERM is the termination on the DIMM and not controlled by the processor. Refer to the applicable DIMM datasheet.
8. The minimum and maximum values for these signals are programmable by BIOS to one of the pairs.
9. COMP resistance must be provided on the system board with 1% resistors. DDR01_RCOMP[2:0] and DDR23_RCOMP[2:0]
resistors are terminated to VSS.
10. Input leakage current is specified for all DDR3 signals.
11. DRAM_PWR_OK_C{01/23} must have a maximum of 30 ns rise or fall time over VCCD * 0.55 +300mV and -200mV and the
edge must be monotonic.
12. The DDR01/23_RCOMP error tolerance is ±15% from the compensated value.
13. DRAM_PWR_OK_C{01/23}: Data Scrambling must be enabled for production environments. Disabling Data scrambling can be
used for debug and testing purposes only. Running systems with Data Scrambling off will make the configuration out of
specification. For details, refer to the processor Datasheet, Volume 2 of 2; see Related Documents section.
Notes:
1. VTTD supplies the PECI interface. PECI behavior does not affect VTTD minimum/maximum specification
2. It is expected that the PECI driver will take into account the variance in the receiver input thresholds and be able to drive its
output within safe limits (-0.150V to 0.275*VTTD for the low level and 0.725*VTTD to VTTD+0.150V for the high level).
3. The leakage specification applies to powered devices on the PECI bus.
4. One node is counted for each client and one node for the system host. Extended trace lengths might appear as additional
nodes.
5. Excessive capacitive loading on the PECI line may slow down the signal rise/fall times and consequently limit the maximum bit
rate at which the interface can operate.
DDR3 Miscellaneous Signals
VIL
Input Low Voltage
DRAM_PWR_OK_C{01/23} ——
0.55*VCCD +
0.2 V2, 3,
11, 13
VIH
Input High Voltage
DRAM_PWR_OK_C{01/23}
0.55*VCCD
+ 0.3 ——V
2, 4, 5,
11, 13
Table 7-14. PECI DC Specifications
Symbol Definition and Conditions Min Max Units Figure Notes1
VIn Input Voltage Range -0.150 VTT V— —
VHysteresis Hysteresis 0.100 * VTT —V——
VNNegative-edge threshold voltage 0.275 * VTT 0.500 * VTT V7-1 2
VPPositive-edge threshold voltage 0.550 * VTT 0.725 * VTT V7-1 2
ISOURCE
High level output source
VOH = 0.75 * VTT
-6.0 — mA — —
ILeak+
High impedance state leakage to VTTD (Vleak =
VOL) 50 200 μA— 3
RON Buffer On Resistance 20 36 —
CBus Bus capacitance per node N/A 10 pF — 4, 5
VNoise Signal noise immunity above 300 MHz 0.100 * VTT N/A Vp-p ——
Output Edge Rate (50 ohm to VSS, between VIL
and VIH)1.5 4 V/ns — —
Table 7-13. DDR3 and DDR3L Signal DC Specifications (Sheet 2 of 2)
Symbol Parameter Min Typ Max Units Notes1