Datasheet 47
Signal Descriptions
6.7 Serial Voltage Identification (SVID) Signals6.8 Processor Asynchronous Sideband and Miscellaneous Signals
TDO Test Data Out: This signal transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.
TMS Test Mode Select: This signal is a JTAG specification support signal used by
debug tools.
TRST_N Test Reset: This signal resets the Test Access Port (TAP) logic. TRST_N must be
driven low during power on Reset.

Table 6-11. Serial Voltage Identification (SVID) Signals

Signal Name Description
SVIDALERT_N Serial VID alert
SVIDCLK Serial VID clock
SVIDDATA Serial VID data out

Table 6-12. Processor Asynchronous Sideband Signals (Sheet 1 of 3)

Signal Name Description
BIST_ENABLE
BIST Enable Strap: This input allows the platform to enable or disable built-in
self test (BIST) on the processor. This signal is pulled up on the die (refer to
Table 7-6 for details).
CAT_ERR_N
Catastrophic Error: This signal indicates that the system has experienced a fatal
or catastrophic error and cannot continue to operate. The processor will assert
CAT_ERR_N for nonrecoverable machine check errors and other internal
unrecoverable errors. It is expected that every processor in the system will wire-
OR CAT_ERR_N for all processors. Since this is an I/O signal, external agents are
allowed to assert this signal, which will cause the processor to take a machine
check exception. This signal is sampled after PWRGOOD assertion.
On the processor, CAT_ERR_N is used for signaling the following types of errors:
• Legacy MCERRs, CAT_ERR_N is asserted for 16 BCLKs.
• Legacy IERRs, CAT_ERR_N remains asserted until warm or cold reset.
CPU_ONLY_RESET CPU Only Reset: Reserved, not used
ERROR_N[2:0]
Error: These are error status signals for integrated I/O (IIO) unit:
• Error_N0 – Hardware correctable error (no operating system or firmware
action necessary)
• Error_N1 – Non-fatal error (operating system or firmware action required to
contain and recover)
• Error_N2 – Fatal error (system reset likely required to recover)
MEM_HOT_C01_N
MEM_HOT_C23_N
Memory Throttle Control: MEM_HOT_C01_N and MEM_HOT_C23_N signals
have two modes of operation – input and output mode.
Input mode is externally asserted and is used to detect external events (such as
VR_HOT# from the memory voltage regulator) and causes the processor to
throttle the appropriate memory channels.
Output mode is asserted by the processor known as level mode. In level mode,
the output indicates that a particular branch of memory subsystem is hot.
MEM_HOT_C01_N is used for memory channels 0 and 1 while MEM_HOT_C23_N
is used for memory channels 2 and 3.
PMSYNC Power Management Sync: A sideband signal to communicate power
management status from the Platform Controller Hub (PCH) to the processor.

Table 6-10. Joint Test Action Group (JTAG) and Test Access Port (TAP) Signals (Sheet 2 of

2)

Signal Name Description