Datasheet 53
Electrical Specifications
Clock multiplying within the processor is provided by the internal phase locked loop
(PLL) that requires a constant frequency BCLK{0/1}_DP, BCLK{0/1}_DN input, with
exceptions for spread spectrum clocking. DC specifications for the BCLK{0/1}_DP,
BCLK{0/1}_DN inputs are provided in Table 7-15.

7.1.5.1 PLL Power Supply

An on-die PLL filter solution is implemented on the processor. Refer to Table 7-10 for
DC specifications.
7.1.6 Joint Test Action Group (JTAG) and Test Access Port (TAP) Signals
Due to the voltage levels supported by other components in the JTAG and Test Access
Port (TAP) logic, Intel recommends the processor be first in the TAP chain, followed by
any other components within the system. A translation buffer should be used to
connect to the rest of the chain, unless one of the other components is capable of
accepting an input of the appropriate voltage. Two copies of each signal may be
required with each driving a different voltage level.
7.1.7 Processor Sideband Signals
The processor includes asynchronous sideband signals that provide asynchronous
input, output or I/O signals between the processor and the platform or PHC.Details are
in Table 7-5.
All processor asynchronous sideband input signals are required to be asserted/de-
asserted for a defined number of BCLKs for the processor to recognize the proper signal
state.
7.1.8 Power, Ground and Sense Signals
Processors also include various other signals including power/ground and sense points.
Details are in Table 7-5.

7.1.8.1 Power and Ground Lands

All VCC, VCCPLL, VSA, VCCD, VTTA, and VTTD lands must be connected to their
respective processor power planes, while all VSS lands must be connected to the
system ground plane.
For clean on-chip power distribution, processors include lands for all required voltage
supplies. The lands are listed in Table 7-1.