Interfaces
18 Datasheet
2Interfaces
This chapter describes the functional behaviors supported by the processor. Topics
covered include:
• System Memory Interface
• PCI Express* Interface
• Direct Media Interface 2 (DMI2) / PCI Express* Interface
• Platform Environment Control Interface (PECI)

2.1 System Memory Interface

2.1.1 System Memory Technology Support

The Integrated Memory Controller (IMC) supports DDR3 protocols with four
independent 64-bit memory channels and supports 1 unbuffered DIMM per channel.

2.1.2 System Memory Timing Support

The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and
command signal mode timings on the main memory interface:
• tCL = CAS Latency
• tRCD = Activate Command to READ or WRITE Command delay
• tRP = PRECHARGE Command Period
• CWL = CAS Write Latency
• Command Signal modes = 1n indicates a new command may be issued every clock
and 2n indicates a new command may be issued every 2 clocks. Command launch
mode programming depends on the transfer rate and memory configuration.