Datasheet 35
Power Management
4.2.4 Core C-states
The following are general rules for all core C-states, unless specified otherwise:
• A core C-state is determined by the lowest numerical thread state (such as, Thread
0 requests C1E while Thread 1 requests C3, resulting in a core C1E state). See
Table 4-6.
• A core transitions to C0 state when:
— an interrupt occurs.
— there is an access to the monitored address if the state was entered using an
MWAIT instruction.
• For core C1/C1E, and core C3, an interrupt directed toward a single thread wakes
only that thread. However, since both threads are no longer at the same core
C-state, the core resolves to C0.
• An interrupt only wakes the target thread for both C3 and C6 states. Any interrupt
coming into the processor package may wake any core.

4.2.4.1 Core C0 State

The normal operating state of a core where code is being executed.

4.2.4.2 Core C1/C1E State

C1/C1E is a low-power state entered when all threads within a core execute a HLT or
MWAIT(C1/C1E) instruction.
A System Management Interrupt (SMI) handler returns execution to either Normal
state or the C1/C1E state. See the Intel® 64 and IA-32 Architecture Software
Developer’s Manual, Volume 3A/3B: System Programmer’s Guide for more information.
While a core is in C1/C1E state, it processes bus snoops and snoops from other
threads. For more information on C1E, see Section 4.2.5.2.

4.2.4.3 Core C3 State

Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to
the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its
L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while
maintaining its architectural state. All core clocks are stopped at this point. Because the
core caches are flushed, the processor does not wake any core that is in the C3 state
when either a snoop is detected or when another core accesses cacheable memory.

4.2.4.4 Core C6 State

Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an
MWAIT(C6) instruction. Before entering core C6, the core saves its architectural state
to a dedicated SRAM. Once complete, a core will have its voltage reduced to zero volts.
In addition to flushing core caches, the core architecture state is saved to the uncore.
Once the core state save is completed, core voltage is reduced to zero. During exit, the
core is powered on and its architectural state is restored.

4.2.4.5 Core C7 State

Individual threads of a core can enter the C7 state by initiating a P_LVL4 I/O read to
the P_BLK or by an MWAIT(C7) instruction. Core C7 and core C7 substate are the same
as Core C6. The processor does not support LLC flush under any condition.