Datasheet 39
Power Management

4.2.5.5 Package C6 State

A processor enters the package C6 low-power state when:
• At least one core is in the C6 state.
• The other cores are in a C6 or lower power state, and the processor has been
granted permission by the platform.
• L3 shared cache retains context and becomes inaccessible in this state.
• Additional power savings actions, as allowed by the exit latency requirements,
include putting PCIe* links in L1, the uncore is not available, further voltage
reduction can be taken.
In package C6 state, all cores have saved their architectural state and have had their
core voltages reduced to zero volts. The LLC retains context, but no accesses can be
made to the LLC in this state; the cores must break out to the internal state package
C2 for snoops to occur.

4.2.6 Package C-State Power Specifications

The following table lists the processor package C-state power specifications for various
processor SKUs.
The C-state power specification is based on post-silicon validation results. The
processor case temperature is assumed at 50 °C for all C-states. Most of the idle power
is attributed to the significant increase in higher speed I/O interfaces for the processor
(PCIe*, DDR3).
Notes:
1. SKUs are subject to change. Contact your Intel Field Representative to obtain the latest SKU information.
2. Package C1E power specified at TCASE = 60 oC
3. Package C3/C6 power specified at TCASE = 50 oC
4.3 System Memory Power Management
The DDR3 power states can be summarized as the following:
• Normal operation (highest power consumption).
• CKE Power-Down: Opportunistic, per rank control after idle time. There may be
different levels.
— Active Power-Down.
— Pre-charge Power-Down with Fast Exit.
— Pre-charge power Down with Slow Exit.
• Self-Refresh: In this mode no transaction is executed. The DDR consumes the
minimum possible power.
Table 4-10. Package C-State Power Specifications
TDP SKUs1C1E (W)2C3 (W)3C6 (W)3
6-Core
130W (6-core) 53 28 13
4-Core
130W (4-core) 53 28 13