Intel BX80633I74820K, BX80633I74930K Table 7-17. Joint Test Action Group (JTAG) and Test Access Point (TAP) Signals DC Specifications , Table 7-18. Serial VID Interface (SVID) DC Specifications

Electrical Specifications
70 Datasheet
Note:
1. These signals are measured between VIL and VIH.
2. The signal edge rate must be met or the signal must transition monotonically to the asserted state.
Notes:
1. VTT refers to instantaneous VTT
.
2. Measured at 0.31*VTT
3. Vin between 0V and VTT
4. These are measured between VIL and VIH.
5. The signal edge rate must be met or the signal must transition monotonically to the asserted state.
Table 7-17. Joint Test Action Group (JTAG) and Test Access Point (TAP) Signals DC
Specifications
Symbol Parameter Min Max Units Notes
VIL Input Low Voltage — 0.3*VTT V
VIH Input High Voltage 0.7*VTT —V
VIL Input Low Voltage: PREQ_N — 0.4*VTT V
VIH Input High Voltage: PREQ_N 0.8*VTT —V
VOL Output Low Voltage — 0.2*VTT V
VHysteresis Hysteresis 0.1*VTT —V
RON
Buffer On Resistance
BPM_N[7:0], PRDY_N, TDO 414
IIL Input Leakage Current 50 200 A
Input Edge Rate
Signals: BPM_N[7:0], EAR_N, PREQ_N, TCK, TDI,
TMS, TRST_N
0.05 — V/ns 1, 2
Output Edge Rate (50 ohm to VTT)
Signal: BPM_N[7:0], PRDY_N, TDO 0.2 1.5 V/ns 1
Table 7-18. Serial VID Interface (SVID) DC Specifications
Symbol Parameter Min Typ Max Units Notes
VTT Processor I/O Voltage VTT – 3% 1.0 VTT + 3% V
VIL
Input Low Voltage
Signals SVIDDATA, SVIDALERT_N — — 0.4*VTT V1
VIH
Input High Voltage
Signals SVIDDATA, SVIDALERT_N 0.7*VTT ——V1
VOL
Output Low Voltage
Signals SVIDCLK, SVIDDATA — — 0.3*VTT V1
VHysteresis Hysteresis 0.05*VTT ——V1
RON
Buffer On Resistance
Signals SVIDCLK, SVIDDATA 4—14W2
IIL Input Leakage Current ±50 — ±200 A3
Input Edge Rate
Signal: SVIDALERT_N 0.05 — — V/ns 4, 5
Output Edge Rate (50 ohm to VTT) 0.20 — 1.5 V/ns 4