Texas Instruments TMS320DM643x Clock Management, Module Clock ON/OFF, PLL Bypass and Power Down

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Clock Management

7.3Clock Management

7.3.1 Module Clock ON/OFF

The module clock on/off feature allows software to disable clocks to module individually, in order to reduce the module's active power consumption to 0. The DM643x DMP is designed in full static CMOS; thus, when a module clock stops, the module's state is preserved. When the clock is restarted, the module resumes operating from the stopping point.

Note: Stopping clocks to a module only affects active power consumption, it does not affect leakage power consumption.

If a module's clock(s) is stopped while being accessed, the access may not occur, and could potentially lock-up the device. User must ensure that all of the transactions to the module are finished prior to stopping the clocks. The power and sleep controller (PSC) controls module clock gating. The PSC provides some protection against system hang by monitoring the internal bus activity—it only gates internal clock to the module after checking that there is no access to the module from the internal bus.

The procedure to turn module clocks on/off using the PSC is described in Chapter 6. Furthermore, special consideration must be given to DSP clock on/off. The procedure to turn the DSP clock on/off is further described in Section 7.4.2.

Some peripherals provide additional power saving features by clock gating components within its module boundary. See peripheral-specific user's guide for more details on these additional power saving features.

7.3.2 Module Clock Frequency Scaling

Module clock frequency is scalable by programming the PLL's multiply and divide parameters. Reducing the clock frequency reduces the active switching power consumption linearly with frequency. It has no impact on leakage power consumption.

Chapter 4 and Chapter 5 describe the how to program the PLL frequency and the frequency constraints.

7.3.3 PLL Bypass and Power Down

You can bypass the PLLs in the DM643x DMP. Bypassing the PLLs sends the PLL reference clock (MXI/CLKIN) instead of the PLL output (PLLOUT) to the SYSCLK dividers (PLLDIVn) of the PLLC. The PLL reference clock is typically at 27 MHZ; therefore, you can use this mode to reduce the core and module clock frequencies to very low maintenance levels without using the PLL during periods of very low system activity. Furthermore, you can power-down the PLL when bypassing it to save additional active power.

Chapter 4 and Chapter 5 describe PLL bypass and PLL power down.

SPRU978E–March 2008 Power Management 79

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