Texas Instruments TMS320DM643x manual Steps for Changing PLL2 Frequency

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PLL2 Control

5.3.2 Steps for Changing PLL2 Frequency

The PLLC2 is programmed similarly to the PLLC1. Refer to the appropriate subsection on how to program the PLL2 clocks:

∙If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), follow the full PLL initialization procedure in Section 5.3.2.2 to initialize the PLL.

∙If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0), follow the sequence in Section 5.3.2.3 to change the PLL multiplier.

∙If the PLL is already running at a desired multiplier and you only want to change the SYSCLK dividers, follow the sequence in Section 5.3.2.4.

Note that the PLL is powered down after the following device-level global resets:

∙Power-on Reset (POR)

∙Warm Reset (RESET)

∙Max Reset

In addition, note that the PLL2 frequency directly affects the DDR2 memory controller and the VPSS VPBE clock source (if PLLC2 SYSCLK2 is selected as the VPBE clock source). The DDR2 memory controller requires special sequences to be followed before and after you change the PLL2 frequency. You must follow the additional considerations for the DDR2 memory controller in Section 5.3.2.1 in order to not corrupt DDR2 operation.

5.3.2.1DDR2 Considerations When Modifying PLL2 Frequency

Before changing PLL2 and/or PLLC2 frequency, you must take into account the DDR2 memory controller requirements. If the DDR2 memory controller is used in the system, follow the additional steps in this section to change PLL2 and/or PLLC2 frequency without corrupting DDR2 operation.

∙If the DDR2 memory controller is in reset when you desire to change the PLL2 frequency, follow the steps in Section 5.3.2.1.1.

∙If the DDR2 memory controller is already out of reset when you desire to change the PLL2 frequency, follow the steps in Section 5.3.2.1.2.

5.3.2.1.1 PLL2 Frequency Change Steps When DDR2 Memory Controller is In Reset

This section discusses the steps to change the PLL2 frequency when the DDR2 memory controller is in reset. Note that the DDR2 memory controller is in reset after these device-level global resets: power-on reset, warm reset, max reset.

1.Leave the DDR2 memory controller in reset.

2.Program the PLL2 clocks by following the steps in the appropriate section: Section 5.3.2.2, Section 5.3.2.3, or Section 5.3.2.4. (Discussion in Section 5.3.2 explains which is the appropriate subsection).

3.Initialize the DDR2 memory controller. The steps for DDR2 memory controller initialization are found in the TMS320DM643x DMP DDR2 Memory Controller User's Guide (SPRU986).

5.3.2.1.2 PLL2 Frequency Change Steps When DDR2 Memory Controller is Out of Reset

This section discusses the steps to change the PLL2 frequency when the DDR2 memory controller is already out of reset.

	1.	Stop DDR2 memory controller accesses and purge any outstanding requests.
	2.	Put the DDR2 memory in self-refresh mode and stop the DDR2 memory controller clock. The DDR2
		memory controller clock shut down sequence is in the TMS320DM643x DMP DDR2 Memory Controller
		User's Guide (SPRU986).
	3.	Program the PLL2 clocks by following the steps in the appropriate section: Section 5.3.2.2,
		Section 5.3.2.3, or Section 5.3.2.4. (Discussion in Section 5.3.2 explains which is the appropriate
		subsection).
	4.	Re-enable the DDR2 memory controller clock. The DDR2 memory controller clock on sequence is in
		the TMS320DM643x DMP DDR2 Memory Controller User's Guide (SPRU986).
44	PLL Controller		SPRU978E–March 2008

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