Possible Clocking Modes | Texas Instruments TMS320DM643x instruction

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Clock Domains

Table 4-6. Possible Clocking Modes

VPSS_CLKCTL.MUXSEL Bit	Clocking Mode	Description
0	MXI mode	Both the VENC and the DAC get their clock from PLLC1 SYSCLKBP, which
		defaults to the MXI 27 MHZ crystal input divide by 1.
1h	PLL2 mode	The PLL2 (divided-down) generates a 54 MHZ clock. Both the DAC and the
		VENC receive the 54 MHZ. The VENC can optionally divide it by 2 to create a
		27 MHZ clock. Note this mode requires the DDR2 clock setting (from PLL2) to
		be an even multiple of 27 MHZ so that an integer divisor can be used to
		create the 54 MHZ DAC clock. Thus, this mode limits the available DDR2
		clock frequencies.
2h	VPBECLK mode	Both the DAC and the VENC receive the VPBECLK. The VENC has the
		option of dividing it by 2 for progressive scan support driving in 54 MHZ on
		VPBECLK.
3h	PCLK mode	The VENC receives the PCLK. The DAC receives no clock, and should be
		disabled. PCLK can be inverted for negative edge support, selectable by a
		memory-mapped register bit.

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Device Clocking

SPRU978E–March 2008

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Image 36

Texas Instruments TMS320DM643x manual Possible Clocking Modes, VPSSCLKCTL.MUXSEL Bit Clocking Mode Description

Contents

Reference Guide Submit Documentation Feedback Contents PLL Controller Command Register Pllcmd Reset Boot Modes List of Figures List of Tables Submit Documentation Feedback Read This First About This ManualNotational Conventions Related Documentation From Texas Instruments TMS320C6000, C6000 are trademarks of Texas Instruments Introduction Block Diagram IntroductionPeripherals DSP Subsystem in TMS320DM643x DMP Components of the DSP Subsystem Submit Documentation Feedback TMS320C64x+ Megamodule TMS320C64x+ CPU TMS320C64x+ Megamodule Block Diagram Memory Controllers 1 L1P Controller L1P L1D 2 L1D Controller 3 L2 Controller External Memory Controller EMC Internal DMA Idma Power-Down Controller PDC Internal PeripheralsInterrupt Controller Intc Bandwidth Manager Submit Documentation Feedback System Memory Memory Map Memory Interfaces Overview Memory Map DSP Internal Memory L1P, L1D, L2External Memory Internal Peripherals Memory Interfaces Overview 1 DDR2 External Memory InterfaceExternal Memory Interface Asynchronous Emif Interface Submit Documentation Feedback Device Clocking Overview Clock Domains Overview Clock DomainsCore Domains System Clock Modes and Fixed Ratios for Core Clock Domains Overall Clocking Diagram Hecc Core Frequency Flexibility Example PLL1 Frequencies and Dividers 27 MHZ Clock InputCore Voltage Divider 3 DDR2/EMIF Clock Example PLL2 Frequencies Core Voltage = 4 I/O Domains Peripheral I/O Domain Clock Video Processing Back End VPSSCLKCTL.MUXSEL Bit Clocking Mode Description Possible Clocking Modes PLL Controller PLL Module PLL1 Control Device Clock Generation Steps for Changing PLL1/Core Domain FrequencySystem PLLC1 Output Clocks PLLC1 Output Clock Used by Initialization to PLL Mode from PLL Power Down Changing PLL Multiplier Changing Sysclk Dividers Example 5-1. Calculating Number of Clock Cycles N PLL2 Control DDR PLLC2 Output ClocksPllout Output Clock Used by 2.1 DDR2 Considerations When Modifying PLL2 Frequency Steps for Changing PLL2 Frequency Initialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-2. Calculating Number of Clock Cycles N PLL and Reset Controller List PLL and Reset Controller RegistersPLL and Reset Controller Base Address End Address Size PLL Controller Registers Reset Type Status Register Rstype Reset Type Status Register Rstype Field DescriptionsPeripheral ID Register PID Peripheral ID Register PID Field Descriptions PLL Control Register Pllctl PLL Control Register Pllctl Field Descriptions PLL Multiplier Control Register Pllm PLL Controller Divider 1 Register PLLDIV1PLL Multiplier Control Register Pllm Field Descriptions D1EN PLL Controller Divider 2 Register PLLDIV2 PLL Controller Divider 3 Register PLLDIV3D2EN D3EN Oscillator Divider 1 Register OSCDIV1 OD1EN Bypass Divider Register Bpdiv 13. Bypass Divider Register Bpdiv Field DescriptionsBpden PLL Controller Command Register Pllcmd PLL Controller Status Register PllstatGoset Stable PLL Controller Clock Align Control Register Alnctl ALN2 ALN1ALN3 ALN2 Plldiv Ratio Change Status Register Dchange SYS3 SYS2 SYS1SYS3 Clock Enable Control Register Cken 18. Clock Enable Control Register Cken Field DescriptionsObsen Auxen Obsen Clock Status Register Ckstat 19. Clock Status Register Ckstat Field DescriptionsBpon Obson Auxon Sysclk Status Register Systat 20. Sysclk Status Register Systat Field DescriptionsSYS3ON SYS2ON SYS1ON SYS3ON Power and Sleep Controller Power and Sleep Controller PSC Integration Power Domain and Module Topology DM643x DMP Default Module ConfigurationNumber Module Name Default Module State MDSTAT.STATE Power Domain and Module States Power Domain StatesModule States Module States Local Reset Power Domain State TransitionsExecuting State Transitions Module State Transitions IcePick Emulation Commands IcePick Emulation Support in the PSCPSC Interrupts Interrupt Events Local Reset Emulation Events Interrupt RegistersModule State Emulation Events Power and Sleep Controller PSC Registers Interrupt HandlingPSC Registers Offset Register Description Peripheral Revision and Class Information Register PID Interrupt Evaluation Register IntevalInterrupt Evaluation Register Inteval Field Descriptions Module Error Pending Register 1 MERRPR1 Module Error Clear Register 1 MERRCR1Module Error Pending Register 1 MERRPR1 Field Descriptions Module Error Clear Register 1 MERRCR1 Field Descriptions Power Domain Transition Command Register Ptcmd Power Domain Transition Status Register PtstatGOSTAT0 Power Domain Status 0 Register PDSTAT0 Pordone PORState Pordone Power Domain Control 0 Register PDCTL0 Next Module Status n Register MDSTATn 14. Module Status n Register MDSTATn Field Descriptions Module Control n Register MDCTLn 15. Module Control n Register MDCTLn Field DescriptionsEmuihbie Emurstie Lrst Emuihbie Submit Documentation Feedback Power Management Power Management Features Description PSC and Pllc Overview PLL Bypass and Power Down Clock ManagementModule Clock ON/OFF Module Clock Frequency Scaling DSP Sleep Mode Management DSP Sleep ModesDSP Module Clock ON/OFF DSP Module Clock on 3.3 V I/O Power Down Video DAC Power DownDSP Module Clock Off Submit Documentation Feedback Interrupt Controller Submit Documentation Feedback System Module Device Configuration Device Boot Configuration StatusDevice Identification Pin Multiplexing Control Timer Control Vpss Clock and DAC Control3 DDR2 VTP Control HPI Control Bandwidth Management Bus Master DMA Priority ControlTMS320DM643x DMP Master IDs DSP CFG Edma Transfer Controller Configuration Boot ControlTMS320DM643x DMP Default Master Priorities DSP DMA DSP CFG Emac Submit Documentation Feedback Reset 10.110.2 10.3 Reset Pins Device Configurations at ResetReset Types Type Initiator Effect DSP Reset DSP Local ResetDSP Module Reset Software Reset Disable SwRstDisable Synchronous Reset SyncReset Boot Modes Submit Documentation Feedback Revision History Table A-1. Document Revision HistoryAdditions/Modifications/Deletions Products Applications DSPRfid