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Texas Instruments TMS320DM643x manual 2. C64x+ Cache Memory Architecture, Memory Controllers

Models: TMS320DM643x

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Figure 2-2. C64x+ Cache Memory Architecture

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Memory Controllers

Figure 2-2. C64x+ Cache Memory Architecture

C64x+ CPU

Fetch Path

Data Path

256 bit

L1P	L1P
SRAM	Cache
L1 Program

256 bit

		2 x 64 bit
L1D	L1D	Write
SRAM	Cache	Buffer
	L1 Data	128 bit
		128 bit

256 bit

L2 SRAM	L2 Cache
	L2 Unified Data/Program Memory

64 bit

External Memory

Legend:

addressable memory

cache memory

data paths managed by cache controller

SPRU978E–March 2008

TMS320C64x+ Megamodule

Submit Documentation Feedback

Page 19

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Texas Instruments TMS320DM643x manual 2. C64x+ Cache Memory Architecture, Memory Controllers

Contents

TMS320DM643x DMP DSP Subsystem Reference GuideSubmit Documentation Feedback SPRU978E-MarchContents 6.7.3 Module Error Pending Register 1 MERRPR1 Boot Modes ResetList of Figures List of Tables List of TablesSPRU978E-March List of TablesSubmit Documentation Feedback Notational Conventions Read This FirstPreface About This ManualSubmit Documentation Feedback TMS320C6000, C6000 are trademarks of Texas InstrumentsRead This First SPRU978E-MarchIntroduction Block DiagramIntroduction ChapterFigure 1-1. TMS320DM643x DMP Block Diagram 1.2 Block Diagram1.1 Introduction 1.3.1 Components of the DSP Subsystem 1.3 DSP Subsystem in TMS320DM643x DMPSPRU978E-March IntroductionSubmit Documentation Feedback Internal Peripherals TMS320C64x+ MegamoduleTMS320C64x+ CPU Memory Controllers2.2 TMS320C64x+ CPU 2.1 IntroductionFigure 2-1. TMS320C64x+ Megamodule Block Diagram 2.3.1 L1P Controller 2.3 Memory ControllersMemory Controllers Figure 2-2. C64x+ Cache Memory Architecture2.3.3 L2 Controller 2.3.2 L1D Controller2.3.5 Internal DMA IDMA 2.3.4 External Memory Controller EMC2.4 Internal Peripherals 2.4.2 Power-Down Controller PDC2.4.1 Interrupt Controller INTC 2.4.3 Bandwidth Manager SPRU978E-March TMS320C64x+ MegamoduleSubmit Documentation Feedback Chapter System MemoryMemory Map Memory Interfaces Overview3.1.3 Internal Peripherals 3.1 Memory Map3.1.1 DSP Internal Memory L1P, L1D, L2 3.1.2 External Memory3.2.2.1 Asynchronous EMIF Interface 3.2 Memory Interfaces Overview3.2.1 DDR2 External Memory Interface 3.2.2 External Memory InterfaceSPRU978E-March System MemorySubmit Documentation Feedback Chapter Device ClockingOverview Clock DomainsTable 4-1. System Clock Modes and Fixed Ratios for Core Clock Domains 4.1 Overview4.2 Clock Domains 4.2.1 Core DomainsClock Domains Figure 4-1. Overall Clocking DiagramTable 4-2. Example PLL1 Frequencies and Dividers 27 MHZ Clock Input 4.2.2 Core Frequency FlexibilityTable 4-3. Example PLL2 Frequencies Core Voltage = 4.2.3 DDR2/EMIF ClockTable 4-4. Example PLL2 Frequencies Core Voltage = Table 4-5. Peripheral I/O Domain Clock 4.2.4 I/O DomainsFigure 4-2. VPBE/DAC Clocking 4.2.5 Video Processing Back EndClocking Mode Table 4-6. Possible Clocking ModesClock Domains VPSSCLKCTL.MUXSEL BitPLL2 Control PLL ControllerPLL Module PLL1 Control5.2 PLL1 Control 5.1 PLL ModuleTable 5-1. System PLLC1 Output Clocks 5.2.1 Device Clock Generation5.2.2 Steps for Changing PLL1/Core Domain Frequency Figure 5-1. PLL1 Structure in the TMS320DM643x DMP5.2.2.1 Initialization to PLL Mode from PLL Power Down 5.2.2.2 Changing PLL Multiplier Example 5-1. Calculating Number of Clock Cycles N 5.2.2.3 Changing SYSCLK DividersTable 5-2. DDR PLLC2 Output Clocks 5.3 PLL2 Control5.3.1 Device Clock Generation Figure 5-2. PLL2 Structure in the TMS320DM643x DMP5.3.2 Steps for Changing PLL2 Frequency 5.3.2.1 DDR2 Considerations When Modifying PLL2 Frequency5.3.2.2 Initialization to PLL Mode from PLL Power Down 5.3.2.3 Changing PLL Multiplier Example 5-2. Calculating Number of Clock Cycles N 5.3.2.4 Changing SYSCLK Dividers5.4 PLL Controller Registers Table 5-3. PLL and Reset Controller ListTable 5-4. PLL and Reset Controller Registers PLL and Reset Controller5.4.1 Peripheral ID Register PID 5.4.2 Reset Type Status Register RSTYPEFigure 5-4. Reset Type Status Register RSTYPE Table 5-6. Reset Type Status Register RSTYPE Field DescriptionsPLL Controller Registers 5.4.3 PLL Control Register PLLCTLFigure 5-5. PLL Control Register PLLCTL Table 5-7. PLL Control Register PLLCTL Field DescriptionsTable 5-8. PLL Multiplier Control Register PLLM Field Descriptions 5.4.4 PLL Multiplier Control Register PLLM5.4.5 PLL Controller Divider 1 Register PLLDIV1 Figure 5-6. PLL Multiplier Control Register PLLMFigure 5-9. PLL Controller Divider 3 Register PLLDIV3 5.4.6 PLL Controller Divider 2 Register PLLDIV25.4.7 PLL Controller Divider 3 Register PLLDIV3 Figure 5-8. PLL Controller Divider 2 Register PLLDIV2PLL Controller Registers 5.4.8 Oscillator Divider 1 Register OSCDIV1Figure 5-10. Oscillator Divider 1 Register OSCDIV1 Table 5-12. Oscillator Divider 1 Register OSCDIV1 Field DescriptionsPLL Controller Registers 5.4.9 Bypass Divider Register BPDIVFigure 5-11. Bypass Divider Register BPDIV Table 5-13. Bypass Divider Register BPDIV Field Descriptions5.4.11 PLL Controller Status Register PLLSTAT 5.4.10 PLL Controller Command Register PLLCMDFigure 5-12. PLL Controller Command Register PLLCMD Table 5-14. PLL Controller Command Register PLLCMD Field DescriptionsField 5.4.12 PLL Controller Clock Align Control Register ALNCTLFigure 5-14. PLL Controller Clock Align Control Register ALNCTL PLL Controller RegistersField 5.4.13 PLLDIV Ratio Change Status Register DCHANGEFigure 5-15. PLLDIV Ratio Change Status Register DCHANGE PLL Controller RegistersPLL Controller Registers 5.4.14 Clock Enable Control Register CKENFigure 5-16. Clock Enable Control Register CKEN Table 5-18. Clock Enable Control Register CKEN Field DescriptionsPLL Controller Registers 5.4.15 Clock Status Register CKSTATFigure 5-17. Clock Status Register CKSTAT Table 5-19. Clock Status Register CKSTAT Field DescriptionsPLL Controller Registers 5.4.16 SYSCLK Status Register SYSTATFigure 5-18. SYSCLK Status Register SYSTAT Table 5-20. SYSCLK Status Register SYSTAT Field DescriptionsExecuting State Transitions Power and Sleep ControllerPower Domain and Module Topology Power Domain and Module States6.1 Introduction Figure 6-1. Power and Sleep Controller PSC IntegrationTable 6-1. DM643x DMP Default Module Configuration 6.2 Power Domain and Module TopologyTable 6-2. Module States 6.3 Power Domain and Module States6.3.1 Power Domain States 6.3.2 Module States6.4.2 Module State Transitions 6.3.3 Local Reset6.4.1 Power Domain State Transitions 6.4 Executing State Transitions6.6.1 Interrupt Events Table 6-3. IcePick Emulation Commands6.5 IcePick Emulation Support in the PSC 6.6 PSC Interrupts6.6.2 Interrupt Registers 6.6.1.2 Local Reset Emulation Events6.6.1.1 Module State Emulation Events 6.6.3 Interrupt Handling Table 6-5. Power and Sleep Controller PSC Registers6.7 PSC Registers Figure 6-3. Interrupt Evaluation Register INTEVAL 6.7.1 Peripheral Revision and Class Information Register PID6.7.2 Interrupt Evaluation Register INTEVAL Figure 6-2. Peripheral Revision and Class Information Register PIDTable 6-8. Module Error Pending Register 1 MERRPR1 Field Descriptions 6.7.3 Module Error Pending Register 1 MERRPR16.7.4 Module Error Clear Register 1 MERRCR1 Figure 6-4. Module Error Pending Register 1 MERRPR1Figure 6-7. Power Domain Transition Status Register PTSTAT 6.7.5 Power Domain Transition Command Register PTCMD6.7.6 Power Domain Transition Status Register PTSTAT Figure 6-6. Power Domain Transition Command Register PTCMDPower and Sleep Controller 6.7.7 Power Domain Status 0 Register PDSTAT0Figure 6-8. Power Domain Status 0 Register PDSTAT0 Table 6-12. Power Domain Status 0 Register PDSTAT0 Field DescriptionsPower and Sleep Controller 6.7.8 Power Domain Control 0 Register PDCTL0Figure 6-9. Power Domain Control 0 Register PDCTL0 Table 6-13. Power Domain Control 0 Register PDCTL0 Field DescriptionsTable 6-14. Module Status n Register MDSTATn Field Descriptions Power and Sleep Controller6.7.9 Module Status n Register MDSTATn Figure 6-10. Module Status n Register MDSTATnTable 6-15. Module Control n Register MDCTLn Field Descriptions Power and Sleep Controller6.7.10 Module Control n Register MDCTLn Figure 6-11. Module Control n Register MDCTLnSPRU978E-March Power and Sleep ControllerSubmit Documentation Feedback PSC and PLLC Overview Power Management3.3 V I/O Power Down Video DAC Power Down7.1 Overview Table 7-1. Power Management Features7.2 PSC and PLLC Overview 7.3.2 Module Clock Frequency Scaling 7.3.3 PLL Bypass and Power Down7.3 Clock Management 7.3.1 Module Clock ON/OFF7.4.2.1 DSP Module Clock ON 7.4 DSP Sleep Mode Management7.4.1 DSP Sleep Modes 7.4.2 DSP Module Clock ON/OFF7.6 Video DAC Power Down 7.5 3.3 V I/O Power Down7.4.2.2 DSP Module Clock Off SPRU978E-March Power ManagementSubmit Documentation Feedback Chapter Interrupt ControllerInterrupt Controller SPRU978E-March Interrupt ControllerSubmit Documentation Feedback System Module Device Configuration3.3 V I/O Power-Down Control Boot Control9.2 Device Identification 9.3 Device Configuration9.3.2 Device Boot Configuration Status 9.1 Overview9.5.2 VPSS Clock and DAC Control 9.4 3.3 V I/O Power-Down Control9.5.1 Timer Control 9.5 Peripheral Status and Control9.6.1 Bus Master DMA Priority Control 9.6 Bandwidth ManagementTable 9-1. TMS320DM643x DMP Master IDs 9.7 Boot Control 9.6.2 EDMA Transfer Controller ConfigurationTable 9-2. TMS320DM643x DMP Default Master Priorities SPRU978E-March System ModuleSubmit Documentation Feedback DSP Reset ResetReset Pins Device Configurations at Reset10.1 Overview 10.2 Reset Pins10.3 Device Configurations at Reset Table 10-1. Reset Types10.4.2.1 Software Reset Disable SwRstDisable 10.4 DSP Reset10.4.1 DSP Local Reset 10.4.2 DSP Module Reset10.4.2.2 Synchronous Reset SyncReset Chapter Boot ModesSPRU978E-March Boot ModesSubmit Documentation Feedback SPRU978E-March Revision HistoryAppendix A Table A-1. Document Revision HistoryApplications power.ti.comIMPORTANT NOTICE Products