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Memory Controllers

2.3.2 L1D Controller

The L1D controller is the hardware interface between level 1 data memory (L1D memory) and the other components in the C64x+ Megamodule (for example, C64x+ CPU, L2 controller, and EMC). The L1D controller responds to data requests from the C64x+ CPU and manages transfer operations between L1D memory and the L2 controller and between L1D memory and the EMC.

Refer to the device-specific data manual for the amount of L1D memory on the device. The L1D controller has a register interface that allows you to configure part of the L1D RAM as normal data RAM or as cache. You can configure cache sizes of 0 KB, 4 KB, 8 KB, 16 KB, or 32 KB of the RAM.

The L1D is divided into two regions—denoted L1D region 0 and L1D region 1. This is the L1D architecture on the DM643x DMP:

L1D region 0: On some DM643x devices, this region is populated with mapped memory. If it is populated with memory, this region is shown as “L1D RAM” in the device-specific data manual.

L1D region 1: Populated with memory that can be configured as mapped memory or cache. This region is shown as “L1D RAM/Cache” in the device-specific data manual.

The DM643x DMP does not support the L1D memory protection features of the standard C64x+ Megamodule.

Refer to the TMS320C64x+ DSP Cache User’s Guide (SPRU862) and to the L1D controller section of the TMS320C64x+ DSP Megamodule Reference Guide (SPRU871) for more information on the L1D controller and for a description of its control registers.

2.3.3 L2 Controller

The L2 controller is the hardware interface between level 2 memory (L2 memory) and the other components in the C64x+ Megamodule (for example, L1P controller, L1D controller, and EMC). The L2 controller manages transfer operations between L2 memory and the other memory controllers (L1P controller, L1D controller, and EMC).

Refer to device-specific data manual for the amount of L2 memory on the device. The L2 controller has a register interface that allows you to configure part or all of the L2 RAM as normal RAM or as cache. You can configure cache sizes of 0 KB, 32 KB, 64 KB, or 128 KB of the RAM.

The L2 memory implements two separate memory ports. This is the L2 architecture on the DM643x DMP:

Port 0

Shown as “L2 RAM/Cache” in the device-specific data manual.

Banking scheme: 2 × 128-bit banks

Latency: 1 cycle (0 wait state)

Port 1

Shown as “Boot ROM” in the device-specific data manual.

Banking scheme: 1 × 256-bit bank

Latency: 1 cycle (0 wait state)

The DM643x DMP does not support the L2 memory protection feature of the standard C64x+ Megamodule.

Refer to the TMS320C64x+ DSP Cache User’s Guide (SPRU862) and to the L2 controller section of the TMS320C64x+ DSP Megamodule Reference Guide (SPRU871) for more information on the L2 controller and for a description of its control registers.

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TMS320C64x+ Megamodule

SPRU978E–March 2008

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Texas Instruments TMS320DM643x manual 2 L1D Controller, 3 L2 Controller