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PLL Module
5.1PLL Module
The DM643x DMP has two PLLs (PLL1 and PLL2) that provide clocks to different parts of the system. PLL1 provides clocks (though various dividers) to most of the components of the DM643x DMP. PLL2 is dedicated to the DDR2 port and components for the video processing subsystem (VPSS). The typical reference clock is the 27 MHZ crystal input, as mentioned in Chapter 4.
The PLL controller provides the following:
∙
∙Domain Clocks Alignment
∙Clock Gating
∙PLL power down
The various clock outputs given by the controller are as follows:
∙Domain Clocks: SYSCLK[1:n]
∙Auxiliary Clock from reference clock source: AUXCLK
∙Bypass Domain clock: SYSCLKBP
∙Observe Clock: OBSCLK
Various dividers that can be used on the DM643x DMP are as follows:
∙PLL Controller Dividers (for SYSCLK[1:n]): PLLDIV1, ..., PLLDIVn
∙Bypass Divider (for SYSCLKBP): BPDIV
∙Oscillator Divider (for OBSCLK): OSCDIV1
Various other controls supported are as follows:
∙PLL Multiplier Control: PLLM
∙
5.2PLL1 Control
PLL1 supplies the primary DM643x DMP system clock. Software controls the PLL1 operation through the system PLL controller 1 (PLLC1) registers. The registers used in PLLC1 are listed in Section 5.4.
Figure
∙SYSCLK1: CLKDIV1 Domain
∙SYSCLK2: CLKDIV3 Domain
∙SYSCLK3: CLKDIV6 Domain
∙AUXCLK: CLKIN Domain
∙OBSCLK: CLKOUT0 pin
∙SYSCLKBP: VPBE internal clock source
The PLL1 multiplier is controlled by the PLLM bit of the PLL multiplier control register (PLLM). The PLL1 output clock may be
You are responsible to adhere to the PLLC1 frequency ranges and multiplier/divider ratios specified in the data manual. See also Section 4.2.1 and Section 4.2.2.
At
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