Device Clock Generation | Texas Instruments TMS320DM643x guide

www.ti.com

PLL1 Control

CLKMODE

CLKIN 1

OSCIN 0

Figure 5-1. PLL1 Structure in the TMS320DM643x DMP

		PLLEN
	PLLOUT	PLLDIV1(/1)	SYSCLK1
			SYSCLK1
			(CLKDIV1Domain)
	PLL		(CLKDIV1Domain)
	PLL	1	SYSCLK2
		PLLDIV2(/3)	SYSCLK2
		PLLDIV2(/3)	(CLKDIV3Domain)
			(CLKDIV3Domain)
		0	SYSCLK3
		PLLDIV3(/6)	SYSCLK3
	PLLM	PLLDIV3(/6)	(CLKDIV6Domain)
	PLLM		(CLKDIV6Domain)
			AUXCLK
			(CLKINDomain)
			SYSCLKBP
	BPDIV		(VPSS-VPBR
			ClockSource)
	OSCDIV1		OBSCLK
	OSCDIV1		(CLKOUT0Pin)
			(CLKOUT0Pin)

5.2.1 Device Clock Generation

PLLC1 generates several clocks from the PLL1 output clock for use by the various processors and modules. These are summarized in Table 5-1. SYSCLK1, SYSCLK2, and SYSCLK3 must maintain a fixed frequency ratio requirement, no matter what reference clock (PLL or bypass) or PLL frequency is used.

Table 5-1. System PLLC1 Output Clocks

PLLC1 Output Clock	Used by	Default Divider
SYSCLK1	DSP Subsystem	/1
SYSCLK2	SCR, EDMA, VPSS, CLKDIV3 Domain peripherals	/3
SYSCLK3	CLKDIV6 Domain peripherals	/6
AUXCLK	CLKIN Domain peripherals	NA
OBSCLK	CLKOUT0 source	/1
SYSCLKBP	VPBE clock source	/1

5.2.2 Steps for Changing PLL1/Core Domain Frequency

Refer to the appropriate subsection on how to program the PLL1/Core Domain clocks:

∙If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), follow the full PLL initialization procedure in Section 5.2.2.1 to initialize the PLL.

∙If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0), follow the sequence in Section 5.2.2.2 to change the PLL multiplier.

∙If the PLL is already running at a desired multiplier and you only want to change the SYSCLK dividers, follow the sequence in Section 5.2.2.3.

Note that the PLL is powered down after the following device-level global resets:

∙Power-on Reset (POR)

∙Warm Reset (RESET)

∙Max Reset

SPRU978E–March 2008

PLL Controller

39

Submit Documentation Feedback

Image 39

Texas Instruments TMS320DM643x manual Device Clock Generation, Steps for Changing PLL1/Core Domain Frequency

Contents

Reference Guide Submit Documentation Feedback Contents PLL Controller Command Register Pllcmd Boot Modes Reset List of Figures List of Tables Submit Documentation Feedback Related Documentation From Texas Instruments Read This FirstAbout This Manual Notational Conventions TMS320C6000, C6000 are trademarks of Texas Instruments Introduction Block Diagram IntroductionPeripherals Components of the DSP Subsystem DSP Subsystem in TMS320DM643x DMP Submit Documentation Feedback TMS320C64x+ Megamodule TMS320C64x+ CPU TMS320C64x+ Megamodule Block Diagram 1 L1P Controller Memory Controllers L1D L1P 3 L2 Controller 2 L1D Controller Internal DMA Idma External Memory Controller EMC Power-Down Controller PDC Internal PeripheralsInterrupt Controller Intc Bandwidth Manager Submit Documentation Feedback Memory Map Memory Interfaces Overview System Memory Internal Peripherals Memory MapDSP Internal Memory L1P, L1D, L2 External Memory Asynchronous Emif Interface Memory Interfaces Overview1 DDR2 External Memory Interface External Memory Interface Submit Documentation Feedback Overview Clock Domains Device Clocking System Clock Modes and Fixed Ratios for Core Clock Domains OverviewClock Domains Core Domains Hecc Overall Clocking Diagram Divider Core Frequency FlexibilityExample PLL1 Frequencies and Dividers 27 MHZ Clock Input Core Voltage Example PLL2 Frequencies Core Voltage = 3 DDR2/EMIF Clock Peripheral I/O Domain Clock 4 I/O Domains Video Processing Back End Possible Clocking Modes VPSSCLKCTL.MUXSEL Bit Clocking Mode Description PLL Controller PLL1 Control PLL Module PLLC1 Output Clock Used by Device Clock GenerationSteps for Changing PLL1/Core Domain Frequency System PLLC1 Output Clocks Initialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-1. Calculating Number of Clock Cycles N Changing Sysclk Dividers Output Clock Used by PLL2 ControlDDR PLLC2 Output Clocks Pllout Steps for Changing PLL2 Frequency 2.1 DDR2 Considerations When Modifying PLL2 Frequency Initialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-2. Calculating Number of Clock Cycles N PLL Controller Registers PLL and Reset Controller ListPLL and Reset Controller Registers PLL and Reset Controller Base Address End Address Size Peripheral ID Register PID Field Descriptions Reset Type Status Register RstypeReset Type Status Register Rstype Field Descriptions Peripheral ID Register PID PLL Control Register Pllctl Field Descriptions PLL Control Register Pllctl D1EN PLL Multiplier Control Register PllmPLL Controller Divider 1 Register PLLDIV1 PLL Multiplier Control Register Pllm Field Descriptions D3EN PLL Controller Divider 2 Register PLLDIV2PLL Controller Divider 3 Register PLLDIV3 D2EN OD1EN Oscillator Divider 1 Register OSCDIV1 Bypass Divider Register Bpdiv 13. Bypass Divider Register Bpdiv Field DescriptionsBpden Stable PLL Controller Command Register PllcmdPLL Controller Status Register Pllstat Goset ALN2 PLL Controller Clock Align Control Register AlnctlALN2 ALN1 ALN3 Plldiv Ratio Change Status Register Dchange SYS3 SYS2 SYS1SYS3 Obsen Clock Enable Control Register Cken18. Clock Enable Control Register Cken Field Descriptions Obsen Auxen Obson Auxon Clock Status Register Ckstat19. Clock Status Register Ckstat Field Descriptions Bpon SYS3ON Sysclk Status Register Systat20. Sysclk Status Register Systat Field Descriptions SYS3ON SYS2ON SYS1ON Power and Sleep Controller Power and Sleep Controller PSC Integration Power Domain and Module Topology DM643x DMP Default Module ConfigurationNumber Module Name Default Module State MDSTAT.STATE Module States Power Domain and Module StatesPower Domain States Module States Module State Transitions Local ResetPower Domain State Transitions Executing State Transitions Interrupt Events IcePick Emulation CommandsIcePick Emulation Support in the PSC PSC Interrupts Local Reset Emulation Events Interrupt RegistersModule State Emulation Events Offset Register Description Power and Sleep Controller PSC RegistersInterrupt Handling PSC Registers Peripheral Revision and Class Information Register PID Interrupt Evaluation Register IntevalInterrupt Evaluation Register Inteval Field Descriptions Module Error Clear Register 1 MERRCR1 Field Descriptions Module Error Pending Register 1 MERRPR1Module Error Clear Register 1 MERRCR1 Module Error Pending Register 1 MERRPR1 Field Descriptions Power Domain Transition Command Register Ptcmd Power Domain Transition Status Register PtstatGOSTAT0 Pordone Power Domain Status 0 Register PDSTAT0Pordone POR State Next Power Domain Control 0 Register PDCTL0 14. Module Status n Register MDSTATn Field Descriptions Module Status n Register MDSTATn Emuihbie Module Control n Register MDCTLn15. Module Control n Register MDCTLn Field Descriptions Emuihbie Emurstie Lrst Submit Documentation Feedback Power Management PSC and Pllc Overview Power Management Features Description Module Clock Frequency Scaling PLL Bypass and Power DownClock Management Module Clock ON/OFF DSP Module Clock on DSP Sleep Mode ManagementDSP Sleep Modes DSP Module Clock ON/OFF 3.3 V I/O Power Down Video DAC Power DownDSP Module Clock Off Submit Documentation Feedback Interrupt Controller Submit Documentation Feedback System Module Pin Multiplexing Control Device ConfigurationDevice Boot Configuration Status Device Identification HPI Control Timer ControlVpss Clock and DAC Control 3 DDR2 VTP Control DSP CFG Bandwidth ManagementBus Master DMA Priority Control TMS320DM643x DMP Master IDs DSP DMA DSP CFG Emac Edma Transfer Controller ConfigurationBoot Control TMS320DM643x DMP Default Master Priorities Submit Documentation Feedback 10.3 Reset10.1 10.2 Type Initiator Effect Reset PinsDevice Configurations at Reset Reset Types Software Reset Disable SwRstDisable DSP ResetDSP Local Reset DSP Module Reset Synchronous Reset SyncReset Boot Modes Submit Documentation Feedback Revision History Table A-1. Document Revision HistoryAdditions/Modifications/Deletions Products Applications DSPRfid