Texas Instruments TMS320DM643x manual PLL Multiplier Control Register PLLM

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PLL Controller Registers

5.4.4 PLL Multiplier Control Register (PLLM)

The PLL multiplier control register (PLLM) is shown in Figure 5-6and described in Table 5-8.

Figure 5-6. PLL Multiplier Control Register (PLLM)

31			16
	Reserved
	R-0
15	5	4	0
Reserved			PLLM
R-0			R/W-10h or 13h(1)

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

(1)For PLLC1, PLLM defaults to 10h (PLL1 multiply by 17); for PLLC2, PLLM defaults to 13h (PLL2 multiply by 20).

Table 5-8. PLL Multiplier Control Register (PLLM) Field Descriptions

Bit	Field	Value	Description
31-5	Reserved	0	Reserved
4-0	PLLM	0-1Fh	PLL multiplier select. Multiplier value = PLLM + 1. For example, PLLM = 16 (10h) means multiply by 17.
			See device-specific data manual for valid multiplier values for each PLL.

5.4.5 PLL Controller Divider 1 Register (PLLDIV1)

The PLL controller divider 1 register (PLLDIV1) is shown in Figure 5-7and described in Table 5-9. Divider 1 controls divider for SYSCLK1.

Figure 5-7. PLL Controller Divider 1 Register (PLLDIV1)

31				16
		Reserved
		R-0
15	14	5	4	0
D1EN	Reserved			RATIO
R/W-0	R-0			R/W-0 or 1(1)

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

(1)For PLLC1, RATIO defaults to 0 (PLL1 divide by 1); for PLLC2, RATIO defaults to 1 (PLL2 divide by 2).

Table 5-9. PLL Controller Divider 1 Register (PLLDIV1) Field Descriptions

Bit	Field	Value	Description
31-16	Reserved	0	Reserved
15	D1EN		Divider 1 enable.
		0	Divider 1 is disabled.
		1	Divider 1 is enabled.
14-5	Reserved	0	Reserved
4-0	RATIO	0-1Fh	Divider ratio. Divider value = RATIO + 1. For example, RATIO = 0 means divide by 1.

SPRU978E–March 2008	PLL Controller	51
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