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Texas Instruments TMS320DM643x manual Synchronous Reset SyncReset

Models: TMS320DM643x

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10.4.2.2 Synchronous Reset (SyncReset)

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DSP Reset

∙Host: Assert the DSP local reset (Optional)

–Clear the LRST bit in MDCTL39 to 0. This step is optional. This step asserts the DSP local reset, and is included here so that the DSP does not start running immediately upon it is subsequently enable by the host. Typically, the host only de-asserts local reset to the DSP after it makes sure that code is properly loaded.

10.4.2.2 Synchronous Reset (SyncReset)

In the synchronous reset (SyncReset) state, the DSP’s module reset is asserted and its module clock is enabled. You can use this state to reset the DSP. The following steps describe how to put the DSP in the synchronous reset state:

∙Host: Notify the DSP to prepare for power-down.

∙DSP: Put the DSP in the IDLE state.

–Set PDCCMD to 0001 5555h. PDCMD is a control register in the DSP power-down controller module.

Note: This register can only be written while the DSP is in supervisor mode.

–Execute the IDLE instruction.

∙Host: Sync reset DSP

–Wait for the GOSTAT[0] bit in PTSTAT to clear to 0. You must wait for the power domain to finish any previously initiated transitions before initiating a new transition.

–Set the NEXT bit in MDCTL39 to 1 to prepare the DSP module for a SyncReset transition.

–Set the GO[0] bit in PTCMD to 1 to initiate the state transition.

–Wait for the GOSTAT[0] bit in PTSTAT to clear to 0. The module is safely in the new state only after the GOSTAT[0] bit is cleared to 0.

∙Host: Assert DSP local reset (Optional)

–Clear the LRST bit in MDCTL39 to 0. This step is optional. This step asserts the DSP local reset and is included here so that the DSP does not start running immediately upon it is subsequently enabled by the host. Typically, software de-asserts local reset to the DSP after it makes sure that code is properly loaded.

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SPRU978E–March 2008

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Texas Instruments TMS320DM643x manual Synchronous Reset SyncReset

Contents

Reference Guide TMS320DM643x DMP DSP SubsystemSPRU978E-March Submit Documentation FeedbackContents 6.7.3 Module Error Pending Register 1 MERRPR1 Reset Boot ModesList of Figures List of Tables List of TablesSPRU978E-March List of TablesSubmit Documentation Feedback About This Manual Read This FirstPreface Notational ConventionsSPRU978E-March TMS320C6000, C6000 are trademarks of Texas InstrumentsRead This First Submit Documentation FeedbackChapter Block DiagramIntroduction IntroductionFigure 1-1. TMS320DM643x DMP Block Diagram 1.2 Block Diagram1.1 Introduction 1.3 DSP Subsystem in TMS320DM643x DMP 1.3.1 Components of the DSP SubsystemSPRU978E-March IntroductionSubmit Documentation Feedback Memory Controllers TMS320C64x+ MegamoduleTMS320C64x+ CPU Internal Peripherals2.1 Introduction 2.2 TMS320C64x+ CPUFigure 2-1. TMS320C64x+ Megamodule Block Diagram 2.3 Memory Controllers 2.3.1 L1P ControllerFigure 2-2. C64x+ Cache Memory Architecture Memory Controllers2.3.2 L1D Controller 2.3.3 L2 Controller2.3.4 External Memory Controller EMC 2.3.5 Internal DMA IDMA2.4 Internal Peripherals 2.4.2 Power-Down Controller PDC2.4.1 Interrupt Controller INTC 2.4.3 Bandwidth Manager SPRU978E-March TMS320C64x+ MegamoduleSubmit Documentation Feedback Memory Interfaces Overview System MemoryMemory Map Chapter3.1.2 External Memory 3.1 Memory Map3.1.1 DSP Internal Memory L1P, L1D, L2 3.1.3 Internal Peripherals3.2.2 External Memory Interface 3.2 Memory Interfaces Overview3.2.1 DDR2 External Memory Interface 3.2.2.1 Asynchronous EMIF InterfaceSPRU978E-March System MemorySubmit Documentation Feedback Clock Domains Device ClockingOverview Chapter4.2.1 Core Domains 4.1 Overview4.2 Clock Domains Table 4-1. System Clock Modes and Fixed Ratios for Core Clock DomainsFigure 4-1. Overall Clocking Diagram Clock Domains4.2.2 Core Frequency Flexibility Table 4-2. Example PLL1 Frequencies and Dividers 27 MHZ Clock InputTable 4-3. Example PLL2 Frequencies Core Voltage = 4.2.3 DDR2/EMIF ClockTable 4-4. Example PLL2 Frequencies Core Voltage = 4.2.4 I/O Domains Table 4-5. Peripheral I/O Domain Clock4.2.5 Video Processing Back End Figure 4-2. VPBE/DAC ClockingClock Domains Clocking ModeTable 4-6. Possible Clocking Modes VPSSCLKCTL.MUXSEL BitPLL1 Control PLL ControllerPLL Module PLL2 Control5.1 PLL Module 5.2 PLL1 ControlFigure 5-1. PLL1 Structure in the TMS320DM643x DMP 5.2.1 Device Clock Generation5.2.2 Steps for Changing PLL1/Core Domain Frequency Table 5-1. System PLLC1 Output Clocks5.2.2.1 Initialization to PLL Mode from PLL Power Down 5.2.2.2 Changing PLL Multiplier 5.2.2.3 Changing SYSCLK Dividers Example 5-1. Calculating Number of Clock Cycles NFigure 5-2. PLL2 Structure in the TMS320DM643x DMP 5.3 PLL2 Control5.3.1 Device Clock Generation Table 5-2. DDR PLLC2 Output Clocks5.3.2.1 DDR2 Considerations When Modifying PLL2 Frequency 5.3.2 Steps for Changing PLL2 Frequency5.3.2.2 Initialization to PLL Mode from PLL Power Down 5.3.2.3 Changing PLL Multiplier 5.3.2.4 Changing SYSCLK Dividers Example 5-2. Calculating Number of Clock Cycles NPLL and Reset Controller Table 5-3. PLL and Reset Controller ListTable 5-4. PLL and Reset Controller Registers 5.4 PLL Controller RegistersTable 5-6. Reset Type Status Register RSTYPE Field Descriptions 5.4.2 Reset Type Status Register RSTYPEFigure 5-4. Reset Type Status Register RSTYPE 5.4.1 Peripheral ID Register PIDTable 5-7. PLL Control Register PLLCTL Field Descriptions 5.4.3 PLL Control Register PLLCTLFigure 5-5. PLL Control Register PLLCTL PLL Controller RegistersFigure 5-6. PLL Multiplier Control Register PLLM 5.4.4 PLL Multiplier Control Register PLLM5.4.5 PLL Controller Divider 1 Register PLLDIV1 Table 5-8. PLL Multiplier Control Register PLLM Field DescriptionsFigure 5-8. PLL Controller Divider 2 Register PLLDIV2 5.4.6 PLL Controller Divider 2 Register PLLDIV25.4.7 PLL Controller Divider 3 Register PLLDIV3 Figure 5-9. PLL Controller Divider 3 Register PLLDIV3Table 5-12. Oscillator Divider 1 Register OSCDIV1 Field Descriptions 5.4.8 Oscillator Divider 1 Register OSCDIV1Figure 5-10. Oscillator Divider 1 Register OSCDIV1 PLL Controller RegistersTable 5-13. Bypass Divider Register BPDIV Field Descriptions 5.4.9 Bypass Divider Register BPDIVFigure 5-11. Bypass Divider Register BPDIV PLL Controller RegistersTable 5-14. PLL Controller Command Register PLLCMD Field Descriptions 5.4.10 PLL Controller Command Register PLLCMDFigure 5-12. PLL Controller Command Register PLLCMD 5.4.11 PLL Controller Status Register PLLSTATPLL Controller Registers 5.4.12 PLL Controller Clock Align Control Register ALNCTLFigure 5-14. PLL Controller Clock Align Control Register ALNCTL FieldPLL Controller Registers 5.4.13 PLLDIV Ratio Change Status Register DCHANGEFigure 5-15. PLLDIV Ratio Change Status Register DCHANGE FieldTable 5-18. Clock Enable Control Register CKEN Field Descriptions 5.4.14 Clock Enable Control Register CKENFigure 5-16. Clock Enable Control Register CKEN PLL Controller RegistersTable 5-19. Clock Status Register CKSTAT Field Descriptions 5.4.15 Clock Status Register CKSTATFigure 5-17. Clock Status Register CKSTAT PLL Controller RegistersTable 5-20. SYSCLK Status Register SYSTAT Field Descriptions 5.4.16 SYSCLK Status Register SYSTATFigure 5-18. SYSCLK Status Register SYSTAT PLL Controller RegistersPower Domain and Module States Power and Sleep ControllerPower Domain and Module Topology Executing State TransitionsFigure 6-1. Power and Sleep Controller PSC Integration 6.1 Introduction6.2 Power Domain and Module Topology Table 6-1. DM643x DMP Default Module Configuration6.3.2 Module States 6.3 Power Domain and Module States6.3.1 Power Domain States Table 6-2. Module States6.4 Executing State Transitions 6.3.3 Local Reset6.4.1 Power Domain State Transitions 6.4.2 Module State Transitions6.6 PSC Interrupts Table 6-3. IcePick Emulation Commands6.5 IcePick Emulation Support in the PSC 6.6.1 Interrupt Events6.6.2 Interrupt Registers 6.6.1.2 Local Reset Emulation Events6.6.1.1 Module State Emulation Events 6.6.3 Interrupt Handling Table 6-5. Power and Sleep Controller PSC Registers6.7 PSC Registers Figure 6-2. Peripheral Revision and Class Information Register PID 6.7.1 Peripheral Revision and Class Information Register PID6.7.2 Interrupt Evaluation Register INTEVAL Figure 6-3. Interrupt Evaluation Register INTEVALFigure 6-4. Module Error Pending Register 1 MERRPR1 6.7.3 Module Error Pending Register 1 MERRPR16.7.4 Module Error Clear Register 1 MERRCR1 Table 6-8. Module Error Pending Register 1 MERRPR1 Field DescriptionsFigure 6-6. Power Domain Transition Command Register PTCMD 6.7.5 Power Domain Transition Command Register PTCMD6.7.6 Power Domain Transition Status Register PTSTAT Figure 6-7. Power Domain Transition Status Register PTSTATTable 6-12. Power Domain Status 0 Register PDSTAT0 Field Descriptions 6.7.7 Power Domain Status 0 Register PDSTAT0Figure 6-8. Power Domain Status 0 Register PDSTAT0 Power and Sleep ControllerTable 6-13. Power Domain Control 0 Register PDCTL0 Field Descriptions 6.7.8 Power Domain Control 0 Register PDCTL0Figure 6-9. Power Domain Control 0 Register PDCTL0 Power and Sleep ControllerFigure 6-10. Module Status n Register MDSTATn Power and Sleep Controller6.7.9 Module Status n Register MDSTATn Table 6-14. Module Status n Register MDSTATn Field DescriptionsFigure 6-11. Module Control n Register MDCTLn Power and Sleep Controller6.7.10 Module Control n Register MDCTLn Table 6-15. Module Control n Register MDCTLn Field DescriptionsSPRU978E-March Power and Sleep ControllerSubmit Documentation Feedback 3.3 V I/O Power Down Power ManagementDSP Sleep Mode Management Video DAC Power Down7.1 Overview Table 7-1. Power Management Features7.2 PSC and PLLC Overview 7.3.1 Module Clock ON/OFF 7.3.3 PLL Bypass and Power Down7.3 Clock Management 7.3.2 Module Clock Frequency Scaling7.4.2 DSP Module Clock ON/OFF 7.4 DSP Sleep Mode Management7.4.1 DSP Sleep Modes 7.4.2.1 DSP Module Clock ON7.6 Video DAC Power Down 7.5 3.3 V I/O Power Down7.4.2.2 DSP Module Clock Off SPRU978E-March Power ManagementSubmit Documentation Feedback Chapter Interrupt ControllerInterrupt Controller SPRU978E-March Interrupt ControllerSubmit Documentation Feedback Boot Control Device Configuration3.3 V I/O Power-Down Control System Module9.1 Overview 9.3 Device Configuration9.3.2 Device Boot Configuration Status 9.2 Device Identification9.5 Peripheral Status and Control 9.4 3.3 V I/O Power-Down Control9.5.1 Timer Control 9.5.2 VPSS Clock and DAC Control9.6.1 Bus Master DMA Priority Control 9.6 Bandwidth ManagementTable 9-1. TMS320DM643x DMP Master IDs 9.7 Boot Control 9.6.2 EDMA Transfer Controller ConfigurationTable 9-2. TMS320DM643x DMP Default Master Priorities SPRU978E-March System ModuleSubmit Documentation Feedback Device Configurations at Reset ResetReset Pins DSP ResetTable 10-1. Reset Types 10.2 Reset Pins10.3 Device Configurations at Reset 10.1 Overview10.4.2 DSP Module Reset 10.4 DSP Reset10.4.1 DSP Local Reset 10.4.2.1 Software Reset Disable SwRstDisable10.4.2.2 Synchronous Reset SyncReset Boot Modes ChapterSPRU978E-March Boot ModesSubmit Documentation Feedback Table A-1. Document Revision History Revision HistoryAppendix A SPRU978E-MarchProducts power.ti.comIMPORTANT NOTICE Applications