Texas Instruments TMS320DM643x manual DSP Reset, DSP Local Reset, DSP Module Reset

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DSP Reset

10.4 DSP Reset

Note: The effects of DSP local reset and DSP module reset have not been fully validated; therefore, these resets are not supported and should not be used. Instead, the POR or RESET pins should be used to reset the entire DSP.

With access to the power and sleep controller (PSC) registers, the external host (for example, PCI or HPI) can assert and de-assert DSP local reset and DSP module reset. When DSP local reset is asserted, the DSP’s internal memories (L1P, L1D, and L2) are still accessible. Local reset only resets the DSP CPU. Local reset is useful when the DSP module is in the enable or disable states, since module reset is asserted in the SyncReset and SwRstDisable states and module reset supersedes local reset. The intent of DSP module reset is for the external host to completely reset the DSP. The intent of DSP local reset is to allow the external host to hold the CPU in reset while the host is loading code into the DSP internal memory—this step can be useful after the host puts the DSP in module reset and then subsequently enables the DSP. For more information on the PSC, see Chapter 6. This section describes how to initiate DSP local reset and module reset.

10.4.1 DSP Local Reset

The following steps describe how an external host can assert/de-assert local reset to the DSP:

1.Clear the LRST bit in MDCTL39 to 0 to assert DSP reset.

2.Set the LRST bit in MDCTL39 to 1 to de-assert DSP reset.

10.4.2DSP Module Reset

The external host may program the PSC to assert DSP module reset by placing the DSP in either Software Reset Disable (SwRstDisable) state or Synchronous Reset (SyncReset) state. See Chapter 6 for descriptions of these PSC states.

10.4.2.1 Software Reset Disable (SwRstDisable)

In the software reset disable (SwRstDisable) state, the DSP’s module reset is asserted and its module clock is turned off. You can use this state to reset the DSP. The following steps describe how to put the DSP in the software reset disable state:

∙Host: Notify the DSP to prepare for power-down.

∙DSP: Put the DSP in the IDLE state.

–Set PDCCMD to 0001 5555h. PDCMD is a control register in the DSP power-down controller module.

Note: This register can only be written while the DSP is in its supervisor mode.

–Execute the IDLE instruction if the DSP is in the enable state. IDLE is a program instruction in the C64x+ CPU instruction set. When the CPU executes IDLE, the PDC is notified and will initiate the DSP power-down according to the bits that you set in the PDCCMD (0181 0000h) register. See the TMS320C64x+ DSP Megamodule Reference Guide (SPRU871) for more information on the PDC and the IDLE instruction.

∙Host: Software reset disable DSP.

–Wait for the GOSTAT[0] bit in PTSTAT to clear to 0. You must wait for the power domain to finish any previously initiated transitions before initiating a new transition.

–Clear the NEXT bit in MDCTL39 to 0 to prepare the DSP module for a SwRstDisable transition.

–Set the GO[0] bit in PTCMD to 1 to initiate the state transition.

–Wait for GOSTAT[0] bit in PTSTAT to clear to 0. The module is safely in the new state only after the GOSTAT[0] bit is cleared to 0.

SPRU978E–March 2008 Reset 93

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