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Texas Instruments TMS320DM643x manual PLL Controller Clock Align Control Register ALNCTL, Field

Models: TMS320DM643x

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5.4.12 PLL Controller Clock Align Control Register (ALNCTL)

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PLL Controller Registers

5.4.12 PLL Controller Clock Align Control Register (ALNCTL)

The PLL controller clock align control register (ALNCTL) is shown in Figure 5-14and described in Table 5-16. ALNCTL indicates which SYSCLKs need to be aligned for proper device operation. You should not modify ALNCTL from its default settings.

Figure 5-14. PLL Controller Clock Align Control Register (ALNCTL)

31				16
	Reserved
	R-0
15	3	2	1	0
Reserved		ALN3	ALN2	ALN1
R/W-0h or 3h(1)		R/W-0 or 1(2)	R/W-0 or 1(3)	R/W-0 or 1(4)

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

(1)For PLLC1, this reserved field defaults to 3h; for PLLC2, this reserved field defaults to 0h. User must not oppose the default value.

(2)For PLLC1, ALN3 defaults to 1; for PLLC2, ALN3 is reserved and defaults to 0.

(3)For PLLC1, ALN2 defaults to 1; for PLLC2, ALN2 defaults to 0.

(4)For PLLC1, ALN1 defaults to 1; for PLLC2, ALN1 defaults to 0.

Table 5-16. PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions

Bit	Field	Value	Description
31-3	Reserved	0 or 3	Reserved. User must not oppose the default value.
2	ALN3		SYSCLK3 needs to be aligned to others selected in this register. Not applicable on PLLC2 (this bit is
			reserved).
		0	SYSCLK3 does not need to be aligned.
		1	SYSCLK3 does need to be aligned.
1	ALN2		SYSCLK2 needs to be aligned to others selected in this register.
		0	SYSCLK2 does not need to be aligned.
		1	SYSCLK2 does need to be aligned.
0	ALN1		SYSCLK1 needs to be aligned to others selected in this register.
		0	SYSCLK1 does not need to be aligned.
		1	SYSCLK1 does need to be aligned.

56	PLL Controller	SPRU978E–March 2008
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Texas Instruments TMS320DM643x manual PLL Controller Clock Align Control Register ALNCTL, PLL Controller Registers, Field

Contents

Reference Guide TMS320DM643x DMP DSP SubsystemSPRU978E-March Submit Documentation FeedbackContents 6.7.3 Module Error Pending Register 1 MERRPR1 Reset Boot ModesList of Figures List of Tables List of TablesSubmit Documentation Feedback List of TablesSPRU978E-March Read This First PrefaceAbout This Manual Notational ConventionsTMS320C6000, C6000 are trademarks of Texas Instruments Read This FirstSPRU978E-March Submit Documentation FeedbackBlock Diagram IntroductionChapter Introduction1.1 Introduction 1.2 Block DiagramFigure 1-1. TMS320DM643x DMP Block Diagram 1.3 DSP Subsystem in TMS320DM643x DMP 1.3.1 Components of the DSP SubsystemSubmit Documentation Feedback IntroductionSPRU978E-March TMS320C64x+ Megamodule TMS320C64x+ CPUMemory Controllers Internal Peripherals2.1 Introduction 2.2 TMS320C64x+ CPUFigure 2-1. TMS320C64x+ Megamodule Block Diagram 2.3 Memory Controllers 2.3.1 L1P ControllerFigure 2-2. C64x+ Cache Memory Architecture Memory Controllers2.3.2 L1D Controller 2.3.3 L2 Controller2.3.4 External Memory Controller EMC 2.3.5 Internal DMA IDMA2.4.1 Interrupt Controller INTC 2.4.2 Power-Down Controller PDC2.4 Internal Peripherals 2.4.3 Bandwidth Manager Submit Documentation Feedback TMS320C64x+ MegamoduleSPRU978E-March System Memory Memory MapMemory Interfaces Overview Chapter3.1 Memory Map 3.1.1 DSP Internal Memory L1P, L1D, L23.1.2 External Memory 3.1.3 Internal Peripherals3.2 Memory Interfaces Overview 3.2.1 DDR2 External Memory Interface3.2.2 External Memory Interface 3.2.2.1 Asynchronous EMIF InterfaceSubmit Documentation Feedback System MemorySPRU978E-March Device Clocking OverviewClock Domains Chapter4.1 Overview 4.2 Clock Domains4.2.1 Core Domains Table 4-1. System Clock Modes and Fixed Ratios for Core Clock DomainsFigure 4-1. Overall Clocking Diagram Clock Domains4.2.2 Core Frequency Flexibility Table 4-2. Example PLL1 Frequencies and Dividers 27 MHZ Clock InputTable 4-4. Example PLL2 Frequencies Core Voltage = 4.2.3 DDR2/EMIF ClockTable 4-3. Example PLL2 Frequencies Core Voltage = 4.2.4 I/O Domains Table 4-5. Peripheral I/O Domain Clock4.2.5 Video Processing Back End Figure 4-2. VPBE/DAC ClockingTable 4-6. Possible Clocking Modes Clock DomainsVPSSCLKCTL.MUXSEL Bit Clocking ModePLL Controller PLL ModulePLL1 Control PLL2 Control5.1 PLL Module 5.2 PLL1 Control5.2.1 Device Clock Generation 5.2.2 Steps for Changing PLL1/Core Domain FrequencyFigure 5-1. PLL1 Structure in the TMS320DM643x DMP Table 5-1. System PLLC1 Output Clocks5.2.2.1 Initialization to PLL Mode from PLL Power Down 5.2.2.2 Changing PLL Multiplier 5.2.2.3 Changing SYSCLK Dividers Example 5-1. Calculating Number of Clock Cycles N5.3 PLL2 Control 5.3.1 Device Clock GenerationFigure 5-2. PLL2 Structure in the TMS320DM643x DMP Table 5-2. DDR PLLC2 Output Clocks5.3.2.1 DDR2 Considerations When Modifying PLL2 Frequency 5.3.2 Steps for Changing PLL2 Frequency5.3.2.2 Initialization to PLL Mode from PLL Power Down 5.3.2.3 Changing PLL Multiplier 5.3.2.4 Changing SYSCLK Dividers Example 5-2. Calculating Number of Clock Cycles NTable 5-3. PLL and Reset Controller List Table 5-4. PLL and Reset Controller RegistersPLL and Reset Controller 5.4 PLL Controller Registers5.4.2 Reset Type Status Register RSTYPE Figure 5-4. Reset Type Status Register RSTYPETable 5-6. Reset Type Status Register RSTYPE Field Descriptions 5.4.1 Peripheral ID Register PID5.4.3 PLL Control Register PLLCTL Figure 5-5. PLL Control Register PLLCTLTable 5-7. PLL Control Register PLLCTL Field Descriptions PLL Controller Registers5.4.4 PLL Multiplier Control Register PLLM 5.4.5 PLL Controller Divider 1 Register PLLDIV1Figure 5-6. PLL Multiplier Control Register PLLM Table 5-8. PLL Multiplier Control Register PLLM Field Descriptions5.4.6 PLL Controller Divider 2 Register PLLDIV2 5.4.7 PLL Controller Divider 3 Register PLLDIV3Figure 5-8. PLL Controller Divider 2 Register PLLDIV2 Figure 5-9. PLL Controller Divider 3 Register PLLDIV35.4.8 Oscillator Divider 1 Register OSCDIV1 Figure 5-10. Oscillator Divider 1 Register OSCDIV1Table 5-12. Oscillator Divider 1 Register OSCDIV1 Field Descriptions PLL Controller Registers5.4.9 Bypass Divider Register BPDIV Figure 5-11. Bypass Divider Register BPDIVTable 5-13. Bypass Divider Register BPDIV Field Descriptions PLL Controller Registers5.4.10 PLL Controller Command Register PLLCMD Figure 5-12. PLL Controller Command Register PLLCMDTable 5-14. PLL Controller Command Register PLLCMD Field Descriptions 5.4.11 PLL Controller Status Register PLLSTAT5.4.12 PLL Controller Clock Align Control Register ALNCTL Figure 5-14. PLL Controller Clock Align Control Register ALNCTLPLL Controller Registers Field5.4.13 PLLDIV Ratio Change Status Register DCHANGE Figure 5-15. PLLDIV Ratio Change Status Register DCHANGEPLL Controller Registers Field5.4.14 Clock Enable Control Register CKEN Figure 5-16. Clock Enable Control Register CKENTable 5-18. Clock Enable Control Register CKEN Field Descriptions PLL Controller Registers5.4.15 Clock Status Register CKSTAT Figure 5-17. Clock Status Register CKSTATTable 5-19. Clock Status Register CKSTAT Field Descriptions PLL Controller Registers5.4.16 SYSCLK Status Register SYSTAT Figure 5-18. SYSCLK Status Register SYSTATTable 5-20. SYSCLK Status Register SYSTAT Field Descriptions PLL Controller RegistersPower and Sleep Controller Power Domain and Module TopologyPower Domain and Module States Executing State TransitionsFigure 6-1. Power and Sleep Controller PSC Integration 6.1 Introduction6.2 Power Domain and Module Topology Table 6-1. DM643x DMP Default Module Configuration6.3 Power Domain and Module States 6.3.1 Power Domain States6.3.2 Module States Table 6-2. Module States6.3.3 Local Reset 6.4.1 Power Domain State Transitions6.4 Executing State Transitions 6.4.2 Module State TransitionsTable 6-3. IcePick Emulation Commands 6.5 IcePick Emulation Support in the PSC6.6 PSC Interrupts 6.6.1 Interrupt Events6.6.1.1 Module State Emulation Events 6.6.1.2 Local Reset Emulation Events6.6.2 Interrupt Registers 6.7 PSC Registers Table 6-5. Power and Sleep Controller PSC Registers6.6.3 Interrupt Handling 6.7.1 Peripheral Revision and Class Information Register PID 6.7.2 Interrupt Evaluation Register INTEVALFigure 6-2. Peripheral Revision and Class Information Register PID Figure 6-3. Interrupt Evaluation Register INTEVAL6.7.3 Module Error Pending Register 1 MERRPR1 6.7.4 Module Error Clear Register 1 MERRCR1Figure 6-4. Module Error Pending Register 1 MERRPR1 Table 6-8. Module Error Pending Register 1 MERRPR1 Field Descriptions6.7.5 Power Domain Transition Command Register PTCMD 6.7.6 Power Domain Transition Status Register PTSTATFigure 6-6. Power Domain Transition Command Register PTCMD Figure 6-7. Power Domain Transition Status Register PTSTAT6.7.7 Power Domain Status 0 Register PDSTAT0 Figure 6-8. Power Domain Status 0 Register PDSTAT0Table 6-12. Power Domain Status 0 Register PDSTAT0 Field Descriptions Power and Sleep Controller6.7.8 Power Domain Control 0 Register PDCTL0 Figure 6-9. Power Domain Control 0 Register PDCTL0Table 6-13. Power Domain Control 0 Register PDCTL0 Field Descriptions Power and Sleep ControllerPower and Sleep Controller 6.7.9 Module Status n Register MDSTATnFigure 6-10. Module Status n Register MDSTATn Table 6-14. Module Status n Register MDSTATn Field DescriptionsPower and Sleep Controller 6.7.10 Module Control n Register MDCTLnFigure 6-11. Module Control n Register MDCTLn Table 6-15. Module Control n Register MDCTLn Field DescriptionsSubmit Documentation Feedback Power and Sleep ControllerSPRU978E-March Power Management 3.3 V I/O Power DownVideo DAC Power Down PSC and PLLC Overview7.2 PSC and PLLC Overview Table 7-1. Power Management Features7.1 Overview 7.3.3 PLL Bypass and Power Down 7.3 Clock Management7.3.1 Module Clock ON/OFF 7.3.2 Module Clock Frequency Scaling7.4 DSP Sleep Mode Management 7.4.1 DSP Sleep Modes7.4.2 DSP Module Clock ON/OFF 7.4.2.1 DSP Module Clock ON7.4.2.2 DSP Module Clock Off 7.5 3.3 V I/O Power Down7.6 Video DAC Power Down Submit Documentation Feedback Power ManagementSPRU978E-March Interrupt Controller Interrupt ControllerChapter Submit Documentation Feedback Interrupt ControllerSPRU978E-March Device Configuration 3.3 V I/O Power-Down ControlBoot Control System Module9.3 Device Configuration 9.3.2 Device Boot Configuration Status9.1 Overview 9.2 Device Identification9.4 3.3 V I/O Power-Down Control 9.5.1 Timer Control9.5 Peripheral Status and Control 9.5.2 VPSS Clock and DAC ControlTable 9-1. TMS320DM643x DMP Master IDs 9.6 Bandwidth Management9.6.1 Bus Master DMA Priority Control Table 9-2. TMS320DM643x DMP Default Master Priorities 9.6.2 EDMA Transfer Controller Configuration9.7 Boot Control Submit Documentation Feedback System ModuleSPRU978E-March Reset Reset PinsDevice Configurations at Reset DSP Reset10.2 Reset Pins 10.3 Device Configurations at ResetTable 10-1. Reset Types 10.1 Overview10.4 DSP Reset 10.4.1 DSP Local Reset10.4.2 DSP Module Reset 10.4.2.1 Software Reset Disable SwRstDisable10.4.2.2 Synchronous Reset SyncReset Boot Modes ChapterSubmit Documentation Feedback Boot ModesSPRU978E-March Revision History Appendix ATable A-1. Document Revision History SPRU978E-Marchpower.ti.com IMPORTANT NOTICEProducts Applications