Boot Control, DSP DMA DSP CFG Emac | Texas Instruments TMS320DM643x

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Boot Control

Each switched central resource (SCR) performs prioritization based on the priority level of the master that sends the command. Each bus master's priority is programmed in the chip-level Bus Master Priority Control Registers (MSTPRI0 or MSTPRI1). The default priority level for each bus master is shown in Table 9-2. Application software is expected to modify these values to obtain the desired system performance.

Table 9-2. TMS320DM643x DMP Default Master Priorities

Master	Default Priority
VPSS	0(1)
EDMA Ch 0	0(2)
EDMA Ch 1	0(2)
EDMA Ch 2	0(2)
DSP (DMA)	7(3)
DSP (CFG)	1
EMAC	4
VLYNQ	4
PCI	4

(1)Default value in VPSS PCR register

(2)Default value in EDMA QUEPRI register

(3)Default value in DSP MDMAARBE.PRI field

9.6.2EDMA Transfer Controller Configuration

The EDMA transfer controller default burst size configuration register (EDMATCCFG) in the System module configures the default burst size for the EDMA transfer controllers (EDMATC0, EDMATC1, and EDMATC2). Refer to the device-specific data manual for more information on this register.

9.7Boot Control

The System Module contains the following boot control registers:

∙Device Boot Configuration Register (BOOTCFG)

∙Boot Complete Register (BOOTCMPLT)

∙DSP Boot Address Register (DSPBOOTADDR)

See Chapter 11 and the device-specific data manual for descriptions of these registers.

SPRU978E–March 2008

System Module

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Texas Instruments TMS320DM643x manual Edma Transfer Controller Configuration, Boot Control, DSP DMA DSP CFG Emac

Contents

Reference Guide Submit Documentation Feedback Contents PLL Controller Command Register Pllcmd Boot Modes Reset List of Figures List of Tables Submit Documentation Feedback About This Manual Read This FirstNotational Conventions Related Documentation From Texas Instruments TMS320C6000, C6000 are trademarks of Texas Instruments Introduction Peripherals Block DiagramIntroduction Components of the DSP Subsystem DSP Subsystem in TMS320DM643x DMP Submit Documentation Feedback TMS320C64x+ Megamodule TMS320C64x+ CPU TMS320C64x+ Megamodule Block Diagram 1 L1P Controller Memory Controllers L1D L1P 3 L2 Controller 2 L1D Controller Internal DMA Idma External Memory Controller EMC Interrupt Controller Intc Power-Down Controller PDCInternal Peripherals Bandwidth Manager Submit Documentation Feedback Memory Map Memory Interfaces Overview System Memory DSP Internal Memory L1P, L1D, L2 Memory MapExternal Memory Internal Peripherals 1 DDR2 External Memory Interface Memory Interfaces OverviewExternal Memory Interface Asynchronous Emif Interface Submit Documentation Feedback Overview Clock Domains Device Clocking Clock Domains OverviewCore Domains System Clock Modes and Fixed Ratios for Core Clock Domains Hecc Overall Clocking Diagram Example PLL1 Frequencies and Dividers 27 MHZ Clock Input Core Frequency FlexibilityCore Voltage Divider Example PLL2 Frequencies Core Voltage = 3 DDR2/EMIF Clock Peripheral I/O Domain Clock 4 I/O Domains Video Processing Back End Possible Clocking Modes VPSSCLKCTL.MUXSEL Bit Clocking Mode Description PLL Controller PLL1 Control PLL Module Steps for Changing PLL1/Core Domain Frequency Device Clock GenerationSystem PLLC1 Output Clocks PLLC1 Output Clock Used by Initialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-1. Calculating Number of Clock Cycles N Changing Sysclk Dividers DDR PLLC2 Output Clocks PLL2 ControlPllout Output Clock Used by Steps for Changing PLL2 Frequency 2.1 DDR2 Considerations When Modifying PLL2 Frequency Initialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-2. Calculating Number of Clock Cycles N PLL and Reset Controller Registers PLL and Reset Controller ListPLL and Reset Controller Base Address End Address Size PLL Controller Registers Reset Type Status Register Rstype Field Descriptions Reset Type Status Register RstypePeripheral ID Register PID Peripheral ID Register PID Field Descriptions PLL Control Register Pllctl Field Descriptions PLL Control Register Pllctl PLL Controller Divider 1 Register PLLDIV1 PLL Multiplier Control Register PllmPLL Multiplier Control Register Pllm Field Descriptions D1EN PLL Controller Divider 3 Register PLLDIV3 PLL Controller Divider 2 Register PLLDIV2D2EN D3EN OD1EN Oscillator Divider 1 Register OSCDIV1 Bpden Bypass Divider Register Bpdiv13. Bypass Divider Register Bpdiv Field Descriptions PLL Controller Status Register Pllstat PLL Controller Command Register PllcmdGoset Stable ALN2 ALN1 PLL Controller Clock Align Control Register AlnctlALN3 ALN2 SYS3 Plldiv Ratio Change Status Register DchangeSYS3 SYS2 SYS1 18. Clock Enable Control Register Cken Field Descriptions Clock Enable Control Register CkenObsen Auxen Obsen 19. Clock Status Register Ckstat Field Descriptions Clock Status Register CkstatBpon Obson Auxon 20. Sysclk Status Register Systat Field Descriptions Sysclk Status Register SystatSYS3ON SYS2ON SYS1ON SYS3ON Power and Sleep Controller Power and Sleep Controller PSC Integration Number Module Name Default Module State MDSTAT.STATE Power Domain and Module TopologyDM643x DMP Default Module Configuration Power Domain States Power Domain and Module StatesModule States Module States Power Domain State Transitions Local ResetExecuting State Transitions Module State Transitions IcePick Emulation Support in the PSC IcePick Emulation CommandsPSC Interrupts Interrupt Events Module State Emulation Events Local Reset Emulation EventsInterrupt Registers Interrupt Handling Power and Sleep Controller PSC RegistersPSC Registers Offset Register Description Interrupt Evaluation Register Inteval Field Descriptions Peripheral Revision and Class Information Register PIDInterrupt Evaluation Register Inteval Module Error Clear Register 1 MERRCR1 Module Error Pending Register 1 MERRPR1Module Error Pending Register 1 MERRPR1 Field Descriptions Module Error Clear Register 1 MERRCR1 Field Descriptions GOSTAT0 Power Domain Transition Command Register PtcmdPower Domain Transition Status Register Ptstat Pordone POR Power Domain Status 0 Register PDSTAT0State Pordone Next Power Domain Control 0 Register PDCTL0 14. Module Status n Register MDSTATn Field Descriptions Module Status n Register MDSTATn 15. Module Control n Register MDCTLn Field Descriptions Module Control n Register MDCTLnEmuihbie Emurstie Lrst Emuihbie Submit Documentation Feedback Power Management PSC and Pllc Overview Power Management Features Description Clock Management PLL Bypass and Power DownModule Clock ON/OFF Module Clock Frequency Scaling DSP Sleep Modes DSP Sleep Mode ManagementDSP Module Clock ON/OFF DSP Module Clock on DSP Module Clock Off 3.3 V I/O Power DownVideo DAC Power Down Submit Documentation Feedback Interrupt Controller Submit Documentation Feedback System Module Device Boot Configuration Status Device ConfigurationDevice Identification Pin Multiplexing Control Vpss Clock and DAC Control Timer Control3 DDR2 VTP Control HPI Control Bus Master DMA Priority Control Bandwidth ManagementTMS320DM643x DMP Master IDs DSP CFG Boot Control Edma Transfer Controller ConfigurationTMS320DM643x DMP Default Master Priorities DSP DMA DSP CFG Emac Submit Documentation Feedback 10.1 Reset10.2 10.3 Device Configurations at Reset Reset PinsReset Types Type Initiator Effect DSP Local Reset DSP ResetDSP Module Reset Software Reset Disable SwRstDisable Synchronous Reset SyncReset Boot Modes Submit Documentation Feedback Additions/Modifications/Deletions Revision HistoryTable A-1. Document Revision History Rfid Products ApplicationsDSP