Texas Instruments TMS320DM643x manual Changing SYSCLK Dividers

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PLL1 Control

5.2.2.3Changing SYSCLK Dividers

This section discusses the software sequence to change the SYSCLK dividers. The SYSCLK divider change sequence is also referred to as GO operation, as it involves hitting the GO bit (GOSET bit in PLLCMD) to initiate the divider change. The recommendation is to stop all peripheral operation before changing the SYSCLK dividers, with the exception of the C64x+ DSP and DDR2. The C64x+ DSP must be operational to program the PLL controller. DDR2 operates off of the clock from PLLC2.

1.Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress.

2.Program the RATIO field in PLLDIV1, PLLDIV2, and PLLDIV3 with the desired divide factors. Note that the dividers must maintain a 1:3:6 ratio to satisfy the CLKDIV1, CLKDIV3, CLKDIV6 clock domain requirements. See the device-specific data manual for more details on Clock Domains. In addition, make sure in this step you leave the PLLDIV1.D1EN, PLLDIV2.D2EN, and PLLDIV3.D3EN bits set (default).

3.Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition. During this transition, SYSCLK1, SYSCLK2, and SYSCLK3 are paused momentarily.

4.Wait for N number of PLLDIVn source clock cycles to ensure divider changes have completed. See the following formula for calculating the number of cycles N.

5.Wait for the GOSTAT bit in PLLSTAT to clear to 0.

The following formula should be used to calculate the number of PLLDIVn source clock cycles:

N = (2 × Least Common Multiple [LCM] of all the old SYSCLK divide values) + 50 cycles overhead

Example 5-1. Calculating Number of Clock Cycles N

This example calculates the number of clock cycles N.

∙Settings before divider change:

–PLLDIV1.RATIO = 0 (divide-by-1)

–PLLDIV2.RATIO = 2 (divide-by-3)

–PLLDIV3.RATIO = 5 (divide-by-6)

∙New divider settings:

–PLLDIV1.RATIO = 1 (divide-by-2)

–PLLDIV2.RATIO = 5 (divide-by-6)

–PLLDIV3.RATIO = 11 (divide-by-12)

The least common multiple between the old divider values of /1, /3, and /6 is /6; therefore, the number of cycles N is:

N = (2 × 6) + 50 cycles overhead = 62 PLLDIVn source clock cycles

If PLLC1 is in PLL mode (PLLCTL.PLLEN = 1), the PLLDIVn source clock is the PLL1 output clock. If PLLC1 is in PLL bypass mode (PLLCTL.PLLEN = 0), the PLLDIVn source clock is the device clock source MXI/CLKIN.

42 PLL Controller SPRU978E–March 2008

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