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TMS320DM643x manual Interrupt Controller, SPRU978E-March
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TMS320DM643x
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Block Diagram
1. DM643x DMP Default Module Configuration
Reset
PLL Controller Command Register PLLCMD
Module Error Pending Register 1 MERRPR1
Timer Control
How to
Power-Down Controller PDC
Clock Enable Control Register CKEN
Boot Control
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84
Interrupt Controller
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2008
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Page 83
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Contents
Reference Guide
TMS320DM643x DMP DSP Subsystem
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Contents
6.7.3 Module Error Pending Register 1 MERRPR1
Reset
Boot Modes
List of Figures
List of Tables
List of Tables
List of Tables
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Read This First
Preface
About This Manual
Notational Conventions
TMS320C6000, C6000 are trademarks of Texas Instruments
Read This First
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Block Diagram
Introduction
Chapter
Introduction
1.2 Block Diagram
Figure 1-1. TMS320DM643x DMP Block Diagram
1.1 Introduction
1.3 DSP Subsystem in TMS320DM643x DMP
1.3.1 Components of the DSP Subsystem
Introduction
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TMS320C64x+ Megamodule
TMS320C64x+ CPU
Memory Controllers
Internal Peripherals
2.1 Introduction
2.2 TMS320C64x+ CPU
Figure 2-1. TMS320C64x+ Megamodule Block Diagram
2.3 Memory Controllers
2.3.1 L1P Controller
Figure 2-2. C64x+ Cache Memory Architecture
Memory Controllers
2.3.2 L1D Controller
2.3.3 L2 Controller
2.3.4 External Memory Controller EMC
2.3.5 Internal DMA IDMA
2.4.2 Power-Down Controller PDC
2.4 Internal Peripherals
2.4.1 Interrupt Controller INTC
2.4.3 Bandwidth Manager
TMS320C64x+ Megamodule
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System Memory
Memory Map
Memory Interfaces Overview
Chapter
3.1 Memory Map
3.1.1 DSP Internal Memory L1P, L1D, L2
3.1.2 External Memory
3.1.3 Internal Peripherals
3.2 Memory Interfaces Overview
3.2.1 DDR2 External Memory Interface
3.2.2 External Memory Interface
3.2.2.1 Asynchronous EMIF Interface
System Memory
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Device Clocking
Overview
Clock Domains
Chapter
4.1 Overview
4.2 Clock Domains
4.2.1 Core Domains
Table 4-1. System Clock Modes and Fixed Ratios for Core Clock Domains
Figure 4-1. Overall Clocking Diagram
Clock Domains
4.2.2 Core Frequency Flexibility
Table 4-2. Example PLL1 Frequencies and Dividers 27 MHZ Clock Input
4.2.3 DDR2/EMIF Clock
Table 4-3. Example PLL2 Frequencies Core Voltage =
Table 4-4. Example PLL2 Frequencies Core Voltage =
4.2.4 I/O Domains
Table 4-5. Peripheral I/O Domain Clock
4.2.5 Video Processing Back End
Figure 4-2. VPBE/DAC Clocking
Clocking Mode
Table 4-6. Possible Clocking Modes
Clock Domains
VPSSCLKCTL.MUXSEL Bit
PLL Controller
PLL Module
PLL1 Control
PLL2 Control
5.1 PLL Module
5.2 PLL1 Control
5.2.1 Device Clock Generation
5.2.2 Steps for Changing PLL1/Core Domain Frequency
Figure 5-1. PLL1 Structure in the TMS320DM643x DMP
Table 5-1. System PLLC1 Output Clocks
5.2.2.1 Initialization to PLL Mode from PLL Power Down
5.2.2.2 Changing PLL Multiplier
5.2.2.3 Changing SYSCLK Dividers
Example 5-1. Calculating Number of Clock Cycles N
5.3 PLL2 Control
5.3.1 Device Clock Generation
Figure 5-2. PLL2 Structure in the TMS320DM643x DMP
Table 5-2. DDR PLLC2 Output Clocks
5.3.2.1 DDR2 Considerations When Modifying PLL2 Frequency
5.3.2 Steps for Changing PLL2 Frequency
5.3.2.2 Initialization to PLL Mode from PLL Power Down
5.3.2.3 Changing PLL Multiplier
5.3.2.4 Changing SYSCLK Dividers
Example 5-2. Calculating Number of Clock Cycles N
Table 5-3. PLL and Reset Controller List
Table 5-4. PLL and Reset Controller Registers
PLL and Reset Controller
5.4 PLL Controller Registers
5.4.2 Reset Type Status Register RSTYPE
Figure 5-4. Reset Type Status Register RSTYPE
Table 5-6. Reset Type Status Register RSTYPE Field Descriptions
5.4.1 Peripheral ID Register PID
5.4.3 PLL Control Register PLLCTL
Figure 5-5. PLL Control Register PLLCTL
Table 5-7. PLL Control Register PLLCTL Field Descriptions
PLL Controller Registers
5.4.4 PLL Multiplier Control Register PLLM
5.4.5 PLL Controller Divider 1 Register PLLDIV1
Figure 5-6. PLL Multiplier Control Register PLLM
Table 5-8. PLL Multiplier Control Register PLLM Field Descriptions
5.4.6 PLL Controller Divider 2 Register PLLDIV2
5.4.7 PLL Controller Divider 3 Register PLLDIV3
Figure 5-8. PLL Controller Divider 2 Register PLLDIV2
Figure 5-9. PLL Controller Divider 3 Register PLLDIV3
5.4.8 Oscillator Divider 1 Register OSCDIV1
Figure 5-10. Oscillator Divider 1 Register OSCDIV1
Table 5-12. Oscillator Divider 1 Register OSCDIV1 Field Descriptions
PLL Controller Registers
5.4.9 Bypass Divider Register BPDIV
Figure 5-11. Bypass Divider Register BPDIV
Table 5-13. Bypass Divider Register BPDIV Field Descriptions
PLL Controller Registers
5.4.10 PLL Controller Command Register PLLCMD
Figure 5-12. PLL Controller Command Register PLLCMD
Table 5-14. PLL Controller Command Register PLLCMD Field Descriptions
5.4.11 PLL Controller Status Register PLLSTAT
5.4.12 PLL Controller Clock Align Control Register ALNCTL
Figure 5-14. PLL Controller Clock Align Control Register ALNCTL
PLL Controller Registers
Field
5.4.13 PLLDIV Ratio Change Status Register DCHANGE
Figure 5-15. PLLDIV Ratio Change Status Register DCHANGE
PLL Controller Registers
Field
5.4.14 Clock Enable Control Register CKEN
Figure 5-16. Clock Enable Control Register CKEN
Table 5-18. Clock Enable Control Register CKEN Field Descriptions
PLL Controller Registers
5.4.15 Clock Status Register CKSTAT
Figure 5-17. Clock Status Register CKSTAT
Table 5-19. Clock Status Register CKSTAT Field Descriptions
PLL Controller Registers
5.4.16 SYSCLK Status Register SYSTAT
Figure 5-18. SYSCLK Status Register SYSTAT
Table 5-20. SYSCLK Status Register SYSTAT Field Descriptions
PLL Controller Registers
Power and Sleep Controller
Power Domain and Module Topology
Power Domain and Module States
Executing State Transitions
Figure 6-1. Power and Sleep Controller PSC Integration
6.1 Introduction
6.2 Power Domain and Module Topology
Table 6-1. DM643x DMP Default Module Configuration
6.3 Power Domain and Module States
6.3.1 Power Domain States
6.3.2 Module States
Table 6-2. Module States
6.3.3 Local Reset
6.4.1 Power Domain State Transitions
6.4 Executing State Transitions
6.4.2 Module State Transitions
Table 6-3. IcePick Emulation Commands
6.5 IcePick Emulation Support in the PSC
6.6 PSC Interrupts
6.6.1 Interrupt Events
6.6.1.2 Local Reset Emulation Events
6.6.2 Interrupt Registers
6.6.1.1 Module State Emulation Events
Table 6-5. Power and Sleep Controller PSC Registers
6.6.3 Interrupt Handling
6.7 PSC Registers
6.7.1 Peripheral Revision and Class Information Register PID
6.7.2 Interrupt Evaluation Register INTEVAL
Figure 6-2. Peripheral Revision and Class Information Register PID
Figure 6-3. Interrupt Evaluation Register INTEVAL
6.7.3 Module Error Pending Register 1 MERRPR1
6.7.4 Module Error Clear Register 1 MERRCR1
Figure 6-4. Module Error Pending Register 1 MERRPR1
Table 6-8. Module Error Pending Register 1 MERRPR1 Field Descriptions
6.7.5 Power Domain Transition Command Register PTCMD
6.7.6 Power Domain Transition Status Register PTSTAT
Figure 6-6. Power Domain Transition Command Register PTCMD
Figure 6-7. Power Domain Transition Status Register PTSTAT
6.7.7 Power Domain Status 0 Register PDSTAT0
Figure 6-8. Power Domain Status 0 Register PDSTAT0
Table 6-12. Power Domain Status 0 Register PDSTAT0 Field Descriptions
Power and Sleep Controller
6.7.8 Power Domain Control 0 Register PDCTL0
Figure 6-9. Power Domain Control 0 Register PDCTL0
Table 6-13. Power Domain Control 0 Register PDCTL0 Field Descriptions
Power and Sleep Controller
Power and Sleep Controller
6.7.9 Module Status n Register MDSTATn
Figure 6-10. Module Status n Register MDSTATn
Table 6-14. Module Status n Register MDSTATn Field Descriptions
Power and Sleep Controller
6.7.10 Module Control n Register MDCTLn
Figure 6-11. Module Control n Register MDCTLn
Table 6-15. Module Control n Register MDCTLn Field Descriptions
Power and Sleep Controller
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Power Management
DSP Sleep Mode Management
3.3 V I/O Power Down
Video DAC Power Down
Table 7-1. Power Management Features
7.1 Overview
7.2 PSC and PLLC Overview
7.3.3 PLL Bypass and Power Down
7.3 Clock Management
7.3.1 Module Clock ON/OFF
7.3.2 Module Clock Frequency Scaling
7.4 DSP Sleep Mode Management
7.4.1 DSP Sleep Modes
7.4.2 DSP Module Clock ON/OFF
7.4.2.1 DSP Module Clock ON
7.5 3.3 V I/O Power Down
7.6 Video DAC Power Down
7.4.2.2 DSP Module Clock Off
Power Management
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Interrupt Controller
Chapter
Interrupt Controller
Interrupt Controller
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Device Configuration
3.3 V I/O Power-Down Control
Boot Control
System Module
9.3 Device Configuration
9.3.2 Device Boot Configuration Status
9.1 Overview
9.2 Device Identification
9.4 3.3 V I/O Power-Down Control
9.5.1 Timer Control
9.5 Peripheral Status and Control
9.5.2 VPSS Clock and DAC Control
9.6 Bandwidth Management
9.6.1 Bus Master DMA Priority Control
Table 9-1. TMS320DM643x DMP Master IDs
9.6.2 EDMA Transfer Controller Configuration
9.7 Boot Control
Table 9-2. TMS320DM643x DMP Default Master Priorities
System Module
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Reset
Reset Pins
Device Configurations at Reset
DSP Reset
10.2 Reset Pins
10.3 Device Configurations at Reset
Table 10-1. Reset Types
10.1 Overview
10.4 DSP Reset
10.4.1 DSP Local Reset
10.4.2 DSP Module Reset
10.4.2.1 Software Reset Disable SwRstDisable
10.4.2.2 Synchronous Reset SyncReset
Boot Modes
Chapter
Boot Modes
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Revision History
Appendix A
Table A-1. Document Revision History
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