Texas Instruments TMS320DM643x manual Interrupt Registers, Module State Emulation Events

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PSC Interrupts

The DM643x DMP is a single-processor device. The C64x+ CPU must not program its own module state. The C64x+ CPU module state can only be programmed by an external host (for example, PCI, HPI). As a result, interrupt events listed in Table 6-4can only occur in the scenario where an external host programs the C64x+ CPU module state but the emulator alters that desired state.

6.6.1.1Module State Emulation Events

A module state emulation event occurs when emulation alters the state of a module. Status is reflected in the EMUIHB bit in MDSTATn. In particular, a module state emulation event occurs under the following conditions:

∙When inhibit sleep is asserted by emulation and software attempts to transition the module out of the enable state.

∙When force active is asserted by emulation and module is not already in the enable state.

6.6.1.2Local Reset Emulation Events

A local reset emulation event occurs when emulation alters the local reset of a module. Status is reflected in the EMURST bit in MDSTATn. In particular, a module local reset emulation event occurs under the following conditions:

∙When assert reset is asserted by emulation although software de-asserted the local reset.

∙When wait reset is asserted by emulation.

∙When block reset is asserted by emulation and software attempts to change the state of local reset.

6.6.2Interrupt Registers

The PSC interrupt enable bits are the EMUIHBIE bit in MDCTL39 and the EMURSTIE bit in MDCTL39.

Note: To interrupt the DSP, the power and sleep controller interrupt (PSCINT) must also be enabled in the DSP interrupt controller. See Section 2.4.1 for more information on the interrupt controller.

The PSC interrupt status bits are the M[39] bit in MERRPR1, the EMUIHB bit in MDSTAT39, and the EMURST bit in MDSTAT39. The status bit in MERRPR1 is read by software to determine which module has generated an emulation interrupt, and then software can read the corresponding status bits in MDSTAT39 to determine which event caused the interrupt.

The PSC interrupt clear bit is the M[39] bit in MERRCR1.

The PSC interrupt evaluation bit is the ALLEV bit in INTEVAL. When set, this bit forces the PSC interrupt logic to re-evaluate event status. If any events are still active (if any status bits are set) when the ALLEV bit in INTEVAL is set to 1, the PSCINT is re-asserted to the DSP interrupt controller. Set the ALLEV bit in INTEVAL before exiting your PSCINT interrupt service routine to ensure that you do not miss any PSC interrupts.

See Section 6.7 for complete descriptions of all PSC registers.

SPRU978E–March 2008 Power and Sleep Controller 67

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