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TMS320DM643x
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Device Clocking, Overview Clock Domains
Models:
TMS320DM643x
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Block Diagram
Timer Control
Device Configuration
Reset
IcePick Emulation Commands
Power-Down Controller PDC
Boot Control
DSP Sleep Mode Management
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Chapter 4
SPRU978E–March
2008
Device Clocking
Topic
Page
4.1
Overview
30
4.2
Clock Domains
30
SPRU978E–March
2008
Device Clocking
29
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Contents
Reference Guide
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Contents
PLL Controller Command Register Pllcmd
Boot Modes
Reset
List of Figures
List of Tables
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About This Manual
Read This First
Notational Conventions
Related Documentation From Texas Instruments
TMS320C6000, C6000 are trademarks of Texas Instruments
Introduction
Peripherals
Block Diagram
Introduction
Components of the DSP Subsystem
DSP Subsystem in TMS320DM643x DMP
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TMS320C64x+ Megamodule
TMS320C64x+ CPU
TMS320C64x+ Megamodule Block Diagram
1 L1P Controller
Memory Controllers
L1D
L1P
3 L2 Controller
2 L1D Controller
Internal DMA Idma
External Memory Controller EMC
Interrupt Controller Intc
Power-Down Controller PDC
Internal Peripherals
Bandwidth Manager
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Memory Map Memory Interfaces Overview
System Memory
DSP Internal Memory L1P, L1D, L2
Memory Map
External Memory
Internal Peripherals
1 DDR2 External Memory Interface
Memory Interfaces Overview
External Memory Interface
Asynchronous Emif Interface
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Overview Clock Domains
Device Clocking
Clock Domains
Overview
Core Domains
System Clock Modes and Fixed Ratios for Core Clock Domains
Hecc
Overall Clocking Diagram
Example PLL1 Frequencies and Dividers 27 MHZ Clock Input
Core Frequency Flexibility
Core Voltage
Divider
Example PLL2 Frequencies Core Voltage =
3 DDR2/EMIF Clock
Peripheral I/O Domain Clock
4 I/O Domains
Video Processing Back End
Possible Clocking Modes
VPSSCLKCTL.MUXSEL Bit Clocking Mode Description
PLL Controller
PLL1 Control
PLL Module
Steps for Changing PLL1/Core Domain Frequency
Device Clock Generation
System PLLC1 Output Clocks
PLLC1 Output Clock Used by
Initialization to PLL Mode from PLL Power Down
Changing PLL Multiplier
Example 5-1. Calculating Number of Clock Cycles N
Changing Sysclk Dividers
DDR PLLC2 Output Clocks
PLL2 Control
Pllout
Output Clock Used by
Steps for Changing PLL2 Frequency
2.1 DDR2 Considerations When Modifying PLL2 Frequency
Initialization to PLL Mode from PLL Power Down
Changing PLL Multiplier
Example 5-2. Calculating Number of Clock Cycles N
PLL and Reset Controller Registers
PLL and Reset Controller List
PLL and Reset Controller Base Address End Address Size
PLL Controller Registers
Reset Type Status Register Rstype Field Descriptions
Reset Type Status Register Rstype
Peripheral ID Register PID
Peripheral ID Register PID Field Descriptions
PLL Control Register Pllctl Field Descriptions
PLL Control Register Pllctl
PLL Controller Divider 1 Register PLLDIV1
PLL Multiplier Control Register Pllm
PLL Multiplier Control Register Pllm Field Descriptions
D1EN
PLL Controller Divider 3 Register PLLDIV3
PLL Controller Divider 2 Register PLLDIV2
D2EN
D3EN
OD1EN
Oscillator Divider 1 Register OSCDIV1
Bpden
Bypass Divider Register Bpdiv
13. Bypass Divider Register Bpdiv Field Descriptions
PLL Controller Status Register Pllstat
PLL Controller Command Register Pllcmd
Goset
Stable
ALN2 ALN1
PLL Controller Clock Align Control Register Alnctl
ALN3
ALN2
SYS3
Plldiv Ratio Change Status Register Dchange
SYS3 SYS2 SYS1
18. Clock Enable Control Register Cken Field Descriptions
Clock Enable Control Register Cken
Obsen Auxen
Obsen
19. Clock Status Register Ckstat Field Descriptions
Clock Status Register Ckstat
Bpon
Obson Auxon
20. Sysclk Status Register Systat Field Descriptions
Sysclk Status Register Systat
SYS3ON SYS2ON SYS1ON
SYS3ON
Power and Sleep Controller
Power and Sleep Controller PSC Integration
Number Module Name Default Module State MDSTAT.STATE
Power Domain and Module Topology
DM643x DMP Default Module Configuration
Power Domain States
Power Domain and Module States
Module States
Module States
Power Domain State Transitions
Local Reset
Executing State Transitions
Module State Transitions
IcePick Emulation Support in the PSC
IcePick Emulation Commands
PSC Interrupts
Interrupt Events
Module State Emulation Events
Local Reset Emulation Events
Interrupt Registers
Interrupt Handling
Power and Sleep Controller PSC Registers
PSC Registers
Offset Register Description
Interrupt Evaluation Register Inteval Field Descriptions
Peripheral Revision and Class Information Register PID
Interrupt Evaluation Register Inteval
Module Error Clear Register 1 MERRCR1
Module Error Pending Register 1 MERRPR1
Module Error Pending Register 1 MERRPR1 Field Descriptions
Module Error Clear Register 1 MERRCR1 Field Descriptions
GOSTAT0
Power Domain Transition Command Register Ptcmd
Power Domain Transition Status Register Ptstat
Pordone POR
Power Domain Status 0 Register PDSTAT0
State
Pordone
Next
Power Domain Control 0 Register PDCTL0
14. Module Status n Register MDSTATn Field Descriptions
Module Status n Register MDSTATn
15. Module Control n Register MDCTLn Field Descriptions
Module Control n Register MDCTLn
Emuihbie Emurstie Lrst
Emuihbie
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Power Management
PSC and Pllc Overview
Power Management Features Description
Clock Management
PLL Bypass and Power Down
Module Clock ON/OFF
Module Clock Frequency Scaling
DSP Sleep Modes
DSP Sleep Mode Management
DSP Module Clock ON/OFF
DSP Module Clock on
DSP Module Clock Off
3.3 V I/O Power Down
Video DAC Power Down
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Interrupt Controller
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System Module
Device Boot Configuration Status
Device Configuration
Device Identification
Pin Multiplexing Control
Vpss Clock and DAC Control
Timer Control
3 DDR2 VTP Control
HPI Control
Bus Master DMA Priority Control
Bandwidth Management
TMS320DM643x DMP Master IDs
DSP CFG
Boot Control
Edma Transfer Controller Configuration
TMS320DM643x DMP Default Master Priorities
DSP DMA DSP CFG Emac
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10.1
Reset
10.2
10.3
Device Configurations at Reset
Reset Pins
Reset Types
Type Initiator Effect
DSP Local Reset
DSP Reset
DSP Module Reset
Software Reset Disable SwRstDisable
Synchronous Reset SyncReset
Boot Modes
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Additions/Modifications/Deletions
Revision History
Table A-1. Document Revision History
Rfid
Products Applications
DSP
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