Texas Instruments TMS320DM643x manual Memory Controllers, 2.3.1 L1P Controller

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Memory Controllers

2.3Memory Controllers

The C64x+ Megamodule implements a two-level internal cache-based memory architecture with external memory support. Level 1 memory is split into separate program memory (L1P memory) and data memory (L1D memory). Figure 2-2shows a diagram of the memory architecture. L1P and L1D are configurable as part L1 RAM (normal addressable on-chip memory) and part L1 cache. L1 memory is accessible to the CPU without stalls. Level 2 memory (L2) can also be split into L2 RAM (normal addressable on-chip memory) and L2 cache for caching external memory locations.

The following controllers manage RAM/cache configuration and cache data paths:

∙L1P controller

∙L1D controller

∙L2 controller

∙External memory controller (EMC)

The internal direct memory access (IDMA) controller manages DMA among the L1P, L1D, and L2 memories.

This section briefly describes the cache and DMA controllers. For detailed information about each of these controllers, see the TMS320C64x+ DSP Cache User’s Guide (SPRU862) and the TMS320C64x+ DSP Megamodule Reference Guide (SPRU871).

Note: The C64x+ Megamodule includes the memory controllers; however, the physical L1P, L1D, and L2 memories are not part of the megamodule, even though they reside in the DSP subsystem. Thus, the physical memories are described separately because the C64x+ Megamodule supports a variety of memory configurations. Refer to Section 3.1 for more information on the L1P, L1D, and L2 memory configuration specific to the DM643x DMP.

2.3.1 L1P Controller

The L1P controller is the hardware interface between level 1 program memory (L1P memory) and the other components in the C64x+ Megamodule (for example, C64x+ CPU, L2 controller, and EMC). The L1P controller responds to instruction fetch requests from the C64x+ CPU and manages transfer operations between L1P memory and the L2 controller and between L1P memory and the EMC.

Refer to the device-specific data manual for the amount of L1P memory on the device. The L1P controller has a register interface that allows you to configure part or all of the L1P RAM as normal RAM or as cache. You can configure cache sizes of 0 KB, 4 KB, 8 KB, 16 KB, or 32 KB of the RAM.

The L1P is divided into two regions—denoted L1P region 0 and L1P region 1. This is the L1P architecture on the DM643x DMP:

∙L1P region 0: Not populated with memory.

∙L1P region 1: Populated with memory that can be configured as mapped memory or cache. The L1P region 1 memory has 0 wait state. This region is shown as “L1P RAM/Cache” in the device-specific data manual.

The DM643x DMP does not support the L1P memory protection feature of the standard C64x+ Megamodule.

Refer to the TMS320C64x+ DSP Cache User’s Guide (SPRU862) and to the L1P controller section of the TMS320C64x+ DSP Megamodule Reference Guide (SPRU871) for more information on the L1P controller and for a description of its control registers.

18 TMS320C64x+ Megamodule SPRU978E–March 2008

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