Texas Instruments TMS320DM643x Memory Interfaces Overview, 3.2.1 DDR2 External Memory Interface

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Memory Interfaces Overview

3.2Memory Interfaces Overview

This section describes the different memory interfaces of DM643x DMP. The DM643x DMP supports several memory and external device interfaces, including the following:

∙DDR2 synchronous DRAM

∙Asynchronous EMIF/NOR/NAND Flash

3.2.1 DDR2 External Memory Interface

The DDR2 external memory interface (EMIF) port is a dedicated interface to DDR2 SDRAM. It supports JESD79D-2A standard compliant DDR2 SDRAM devices and can support either 16-bit or 32-bit interfaces.

DDR2 SDRAM plays a key role in a DM643x DMP-based system. Such a system is expected to require a significant amount of high-speed external memory for the following:

∙Buffering input image data from sensors or video sources

∙Intermediate buffering for processing/resizing of image data in the video processing front end (VPFE)

∙Video processing back end (VPBE) display buffers

∙Intermediate buffering for large raw Bayer data image files while performing still camera processing functions

∙Buffering for intermediate data while performing video encode and decode functions

∙Storage of executable firmware for DSP

3.2.2External Memory Interface

The DM643x DMP external memory interface (EMIF) provides an 8-bit data bus, an address bus width of up to 24-bits, and 4 dedicated chip selects, along with memory control signals. These signals are statically multiplexed between the asynchronous EMIF (EMIFA) module that provides asynchronous EMIF and NAND interfaces.

The EMIFA signals are multiplexed with other peripheral signals on the device. Refer to device-specific data manual for details on pin multiplexing.

3.2.2.1Asynchronous EMIF Interface

The asynchronous EMIF (EMIFA) interface provides both the asynchronous EMIF and NAND interfaces. Four chip selects are provided. Each is individually configurable to provide either asynchronous EMIF or NAND support.

∙The asynchronous EMIF mode supports asynchronous devices (RAM, ROM, and NOR Flash)

∙64MB asynchronous address range over 4 chip selects (16MB each)

∙Supports 8-bit data bus width

∙Programmable asynchronous cycle timings

∙Supports extended waits

∙Supports Select Strobe mode

∙Supports TI DSP HPI interface

∙Supports booting DM643x DMP from CS2 (SRAM/NOR Flash)

3.2.2.2NAND Interface

The asynchronous EMIF (EMIFA) interface provides both the asynchronous EMIF and NAND interfaces. Four chip selects are provided and each is individually configurable to provide either EMIFA or NAND support.

∙The NAND mode supports NAND Flash on up to 4 asynchronous chip selects

∙Supports 8-bit data bus width

∙Programmable cycle timings

∙Performs ECC calculation

∙Bootloader code in Boot ROM supports booting of the DM643x DMP from NAND-Flash located at CS2

SPRU978E–March 2008 System Memory 27

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