Bypass Divider Register Bpdiv | Texas Instruments TMS320DM643x

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PLL Controller Registers

5.4.9 Bypass Divider Register (BPDIV)

The bypass divider register (BPDIV) is shown in Figure 5-11and described in Table 5-13. Bypass divider controls divider for SYSCLKBP, dividing down from the MXI/CLKIN clock.

Figure 5-11. Bypass Divider Register (BPDIV)

31				16
		Reserved
		R-0
15	14	5	4	0
BPDEN	Reserved			RATIO
R/W-1	R-0			R/W-0 or 1(1)

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

(1)For PLLC1, RATIO defaults to 0 (MXI/CLKIN divide by 1); for PLLC2, RATIO defaults to 1 (MXI/CLKIN divide by 2).

Table 5-13. Bypass Divider Register (BPDIV) Field Descriptions

Bit	Field	Value	Description
31-16	Reserved	0	Reserved
15	BPDEN		Bypass divider enable.
		0	Bypass divider is disabled.
		1	Bypass divider is enabled.
14-5	Reserved	0	Reserved
4-0	RATIO	0-1Fh	Divider ratio. Divider value = RATIO + 1. For example, RATIO = 0 means divide by 1.

54	PLL Controller	SPRU978E–March 2008
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Image 54

Texas Instruments TMS320DM643x manual Bypass Divider Register Bpdiv Field Descriptions, Bpden

Contents

Reference Guide Submit Documentation Feedback Contents PLL Controller Command Register Pllcmd Reset Boot Modes List of Figures List of Tables Submit Documentation Feedback Notational Conventions Read This FirstAbout This Manual Related Documentation From Texas Instruments TMS320C6000, C6000 are trademarks of Texas Instruments Introduction Block Diagram IntroductionPeripherals DSP Subsystem in TMS320DM643x DMP Components of the DSP Subsystem Submit Documentation Feedback TMS320C64x+ Megamodule TMS320C64x+ CPU TMS320C64x+ Megamodule Block Diagram Memory Controllers 1 L1P Controller L1P L1D 2 L1D Controller 3 L2 Controller External Memory Controller EMC Internal DMA Idma Power-Down Controller PDC Internal PeripheralsInterrupt Controller Intc Bandwidth Manager Submit Documentation Feedback System Memory Memory Map Memory Interfaces Overview External Memory Memory MapDSP Internal Memory L1P, L1D, L2 Internal Peripherals External Memory Interface Memory Interfaces Overview1 DDR2 External Memory Interface Asynchronous Emif Interface Submit Documentation Feedback Device Clocking Overview Clock Domains Core Domains OverviewClock Domains System Clock Modes and Fixed Ratios for Core Clock Domains Overall Clocking Diagram Hecc Core Voltage Core Frequency FlexibilityExample PLL1 Frequencies and Dividers 27 MHZ Clock Input Divider 3 DDR2/EMIF Clock Example PLL2 Frequencies Core Voltage = 4 I/O Domains Peripheral I/O Domain Clock Video Processing Back End VPSSCLKCTL.MUXSEL Bit Clocking Mode Description Possible Clocking Modes PLL Controller PLL Module PLL1 Control System PLLC1 Output Clocks Device Clock GenerationSteps for Changing PLL1/Core Domain Frequency PLLC1 Output Clock Used by Initialization to PLL Mode from PLL Power Down Changing PLL Multiplier Changing Sysclk Dividers Example 5-1. Calculating Number of Clock Cycles N Pllout PLL2 ControlDDR PLLC2 Output Clocks Output Clock Used by 2.1 DDR2 Considerations When Modifying PLL2 Frequency Steps for Changing PLL2 Frequency Initialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-2. Calculating Number of Clock Cycles N PLL and Reset Controller Base Address End Address Size PLL and Reset Controller ListPLL and Reset Controller Registers PLL Controller Registers Peripheral ID Register PID Reset Type Status Register RstypeReset Type Status Register Rstype Field Descriptions Peripheral ID Register PID Field Descriptions PLL Control Register Pllctl PLL Control Register Pllctl Field Descriptions PLL Multiplier Control Register Pllm Field Descriptions PLL Multiplier Control Register PllmPLL Controller Divider 1 Register PLLDIV1 D1EN D2EN PLL Controller Divider 2 Register PLLDIV2PLL Controller Divider 3 Register PLLDIV3 D3EN Oscillator Divider 1 Register OSCDIV1 OD1EN Bypass Divider Register Bpdiv 13. Bypass Divider Register Bpdiv Field DescriptionsBpden Goset PLL Controller Command Register PllcmdPLL Controller Status Register Pllstat Stable ALN3 PLL Controller Clock Align Control Register AlnctlALN2 ALN1 ALN2 Plldiv Ratio Change Status Register Dchange SYS3 SYS2 SYS1SYS3 Obsen Auxen Clock Enable Control Register Cken18. Clock Enable Control Register Cken Field Descriptions Obsen Bpon Clock Status Register Ckstat19. Clock Status Register Ckstat Field Descriptions Obson Auxon SYS3ON SYS2ON SYS1ON Sysclk Status Register Systat20. Sysclk Status Register Systat Field Descriptions SYS3ON Power and Sleep Controller Power and Sleep Controller PSC Integration Power Domain and Module Topology DM643x DMP Default Module ConfigurationNumber Module Name Default Module State MDSTAT.STATE Module States Power Domain and Module StatesPower Domain States Module States Executing State Transitions Local ResetPower Domain State Transitions Module State Transitions PSC Interrupts IcePick Emulation CommandsIcePick Emulation Support in the PSC Interrupt Events Local Reset Emulation Events Interrupt RegistersModule State Emulation Events PSC Registers Power and Sleep Controller PSC RegistersInterrupt Handling Offset Register Description Peripheral Revision and Class Information Register PID Interrupt Evaluation Register IntevalInterrupt Evaluation Register Inteval Field Descriptions Module Error Pending Register 1 MERRPR1 Field Descriptions Module Error Pending Register 1 MERRPR1Module Error Clear Register 1 MERRCR1 Module Error Clear Register 1 MERRCR1 Field Descriptions Power Domain Transition Command Register Ptcmd Power Domain Transition Status Register PtstatGOSTAT0 State Power Domain Status 0 Register PDSTAT0Pordone POR Pordone Power Domain Control 0 Register PDCTL0 Next Module Status n Register MDSTATn 14. Module Status n Register MDSTATn Field Descriptions Emuihbie Emurstie Lrst Module Control n Register MDCTLn15. Module Control n Register MDCTLn Field Descriptions Emuihbie Submit Documentation Feedback Power Management Power Management Features Description PSC and Pllc Overview Module Clock ON/OFF PLL Bypass and Power DownClock Management Module Clock Frequency Scaling DSP Module Clock ON/OFF DSP Sleep Mode ManagementDSP Sleep Modes DSP Module Clock on 3.3 V I/O Power Down Video DAC Power DownDSP Module Clock Off Submit Documentation Feedback Interrupt Controller Submit Documentation Feedback System Module Device Identification Device ConfigurationDevice Boot Configuration Status Pin Multiplexing Control 3 DDR2 VTP Control Timer ControlVpss Clock and DAC Control HPI Control TMS320DM643x DMP Master IDs Bandwidth ManagementBus Master DMA Priority Control DSP CFG TMS320DM643x DMP Default Master Priorities Edma Transfer Controller ConfigurationBoot Control DSP DMA DSP CFG Emac Submit Documentation Feedback 10.2 Reset10.1 10.3 Reset Types Reset PinsDevice Configurations at Reset Type Initiator Effect DSP Module Reset DSP ResetDSP Local Reset Software Reset Disable SwRstDisable Synchronous Reset SyncReset Boot Modes Submit Documentation Feedback Revision History Table A-1. Document Revision HistoryAdditions/Modifications/Deletions Products Applications DSPRfid