Texas Instruments TMS320DM643x DSP Sleep Mode Management, DSP Sleep Modes, DSP Module Clock ON

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DSP Sleep Mode Management

7.4DSP Sleep Mode Management

The C64x+ DSP supports sleep mode management to reduce power:

∙DSP clock can be completely shut off

∙C64x+ Megamodule can be put in sleep mode

– C64x+ CPU can be put in sleep mode

On the DM643x DMP, sleep mode for the DSP internal memories (L1P, L1D, L2) is not supported.

7.4.1 DSP Sleep Modes

The C64x+ Megamodule of the DSP subsystem includes a power-down controller (PDC) that controls the power-down of the C64x+ Megamodule components. Refer to Section 2.4.2 and the TMS320C64x+ DSP Megamodule Reference Guide (SPRU871) for more details on the PDC.

7.4.2 DSP Module Clock ON/OFF

As discussed in Section 7.4.1, the C64x+ Megamodule can clock gate its own components to save power. Additional power saving can be achieved by stopping the clock source to the C64x+ Megamodule by programming the power and sleep controller (PSC) to place the C64x+ Megamodule in Disable state. The C64x+ DSP cannot perform this programming task on its own, because the C64x+ DSP will not be able to complete the PSC programming sequence if the C64x+ DSP clock source is gated in the middle of the process. If stopping the clock source to the C64x+ DSP is desired for additional power saving, an external host is responsible for programming the PSC (for example, via HPI, PCI interfaces) to disable the C64x+ Megamodule. Similarly, in that case the external host is responsible for programming the PSC to enable the C64x+ Megamodule.

7.4.2.1DSP Module Clock ON

In the clock Enable state, the DSP’s module clock is enabled while DSP module reset is de-asserted. This is the state for normal DSP run-time. DSP defaults to Enable state, therefore this DSP Module Clock ON process is typically not needed. This process is only required to wake up the DSP after an external host puts the DSP in Disable state (Section 7.4.2.2).

∙Host: Enable clocks to the DSP.

–Wait for the GOSTAT[0] bit in PTSTAT to clear to 0. You must wait for the power domain to finish any previously initiated transitions before initiating a new transition.

–Set the NEXT bit in MDCTL39 to 3h to prepare the DSP module for an enable transition.

–Set the GO[0] bit in PTCMD to 1 to initiate the state transition.

–Wait for the GOSTAT[0] bit in PTSTAT to clear to 0. The domain is only safely in the new state after the GOSTAT[0] bit is cleared to 0.

–Wait for the STATE bit in MDSTAT39 to change to 3h. The module is only safely in the new state after the STATE bit in MDSTAT39 changes to reflect the new state.

∙Host: Wake the DSP.

–If transitioning from the disable state, trigger a DSP interrupt that has previously been configured as a wake-up interrupt.

Note: This step only applies if you are transitioning from the disable state. If previously in the disable state, a wake-up interrupt must be triggered in order to wake the DSP. This example assumes that the DSP enabled this interrupt before entering its IDLE state. If previously in the software reset disable or synchronous reset state, it is not necessary to wake the DSP because these states assert the DSP module reset. See Chapter 10 for information on the software reset disable and synchronous reset states. See the TMS320C64x+ DSP Megamodule Reference Guide (SPRU871) for more information on DSP interrupts.

80 Power Management SPRU978E–March 2008

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