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Texas Instruments TMS320DM643x Oscillator Divider 1 Register OSCDIV1, PLL Controller Registers

Models: TMS320DM643x

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5.4.8 Oscillator Divider 1 Register (OSCDIV1)

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PLL Controller Registers

5.4.8 Oscillator Divider 1 Register (OSCDIV1)

The oscillator divider 1 register (OSCDIV1) is shown in Figure 5-10and described in Table 5-12. The oscillator divider 1 controls divider for OBSCLK, dividing down from the MXI/CLKIN clock. For PLLC1, the OBSCLK is connected to CLKOUT0 pin. OSCDIV1 only applies to PLLC1, and should not be used on PLLC2.

Figure 5-10. Oscillator Divider 1 Register (OSCDIV1)

31				16
		Reserved
		R-0
15	14	5	4	0
OD1EN	Reserved			RATIO
R/W-1	R-0			R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 5-12. Oscillator Divider 1 Register (OSCDIV1) Field Descriptions

Bit	Field	Value	Description
31-16	Reserved	0	Reserved
15	OD1EN		Oscillator divider 1 enable.
		0	Oscillator divider 1 is disabled.

1Oscillator divider 1 is enabled. For OBSCLK to toggle, both the OD1EN bit and the OBSEN bit in the clock enable control register (CKEN) must be set to 1.

14-5	Reserved	0	Reserved
4-0	RATIO	0-1Fh	Divider ratio. Divider value = RATIO + 1. For example, RATIO = 0 means divide by 1.

SPRU978E–March 2008	PLL Controller	53
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Texas Instruments TMS320DM643x 10. Oscillator Divider 1 Register OSCDIV1, PLL Controller Registers, Field, Description

Contents

TMS320DM643x DMP DSP Subsystem Reference GuideSubmit Documentation Feedback SPRU978E-MarchContents 6.7.3 Module Error Pending Register 1 MERRPR1 Boot Modes ResetList of Figures List of Tables List of TablesSubmit Documentation Feedback List of TablesSPRU978E-March Preface Read This FirstAbout This Manual Notational ConventionsRead This First TMS320C6000, C6000 are trademarks of Texas InstrumentsSPRU978E-March Submit Documentation FeedbackIntroduction Block DiagramChapter Introduction1.1 Introduction 1.2 Block DiagramFigure 1-1. TMS320DM643x DMP Block Diagram 1.3.1 Components of the DSP Subsystem 1.3 DSP Subsystem in TMS320DM643x DMPSubmit Documentation Feedback IntroductionSPRU978E-March TMS320C64x+ CPU TMS320C64x+ MegamoduleMemory Controllers Internal Peripherals2.2 TMS320C64x+ CPU 2.1 IntroductionFigure 2-1. TMS320C64x+ Megamodule Block Diagram 2.3.1 L1P Controller 2.3 Memory ControllersMemory Controllers Figure 2-2. C64x+ Cache Memory Architecture2.3.3 L2 Controller 2.3.2 L1D Controller2.3.5 Internal DMA IDMA 2.3.4 External Memory Controller EMC2.4.1 Interrupt Controller INTC 2.4.2 Power-Down Controller PDC2.4 Internal Peripherals 2.4.3 Bandwidth Manager Submit Documentation Feedback TMS320C64x+ MegamoduleSPRU978E-March Memory Map System MemoryMemory Interfaces Overview Chapter3.1.1 DSP Internal Memory L1P, L1D, L2 3.1 Memory Map3.1.2 External Memory 3.1.3 Internal Peripherals3.2.1 DDR2 External Memory Interface 3.2 Memory Interfaces Overview3.2.2 External Memory Interface 3.2.2.1 Asynchronous EMIF InterfaceSubmit Documentation Feedback System MemorySPRU978E-March Overview Device ClockingClock Domains Chapter4.2 Clock Domains 4.1 Overview4.2.1 Core Domains Table 4-1. System Clock Modes and Fixed Ratios for Core Clock DomainsClock Domains Figure 4-1. Overall Clocking DiagramTable 4-2. Example PLL1 Frequencies and Dividers 27 MHZ Clock Input 4.2.2 Core Frequency FlexibilityTable 4-4. Example PLL2 Frequencies Core Voltage = 4.2.3 DDR2/EMIF ClockTable 4-3. Example PLL2 Frequencies Core Voltage = Table 4-5. Peripheral I/O Domain Clock 4.2.4 I/O DomainsFigure 4-2. VPBE/DAC Clocking 4.2.5 Video Processing Back EndTable 4-6. Possible Clocking Modes Clocking ModeClock Domains VPSSCLKCTL.MUXSEL BitPLL Module PLL ControllerPLL1 Control PLL2 Control5.2 PLL1 Control 5.1 PLL Module5.2.2 Steps for Changing PLL1/Core Domain Frequency 5.2.1 Device Clock GenerationFigure 5-1. PLL1 Structure in the TMS320DM643x DMP Table 5-1. System PLLC1 Output Clocks5.2.2.1 Initialization to PLL Mode from PLL Power Down 5.2.2.2 Changing PLL Multiplier Example 5-1. Calculating Number of Clock Cycles N 5.2.2.3 Changing SYSCLK Dividers5.3.1 Device Clock Generation 5.3 PLL2 ControlFigure 5-2. PLL2 Structure in the TMS320DM643x DMP Table 5-2. DDR PLLC2 Output Clocks5.3.2 Steps for Changing PLL2 Frequency 5.3.2.1 DDR2 Considerations When Modifying PLL2 Frequency5.3.2.2 Initialization to PLL Mode from PLL Power Down 5.3.2.3 Changing PLL Multiplier Example 5-2. Calculating Number of Clock Cycles N 5.3.2.4 Changing SYSCLK DividersTable 5-4. PLL and Reset Controller Registers Table 5-3. PLL and Reset Controller ListPLL and Reset Controller 5.4 PLL Controller RegistersFigure 5-4. Reset Type Status Register RSTYPE 5.4.2 Reset Type Status Register RSTYPETable 5-6. Reset Type Status Register RSTYPE Field Descriptions 5.4.1 Peripheral ID Register PIDFigure 5-5. PLL Control Register PLLCTL 5.4.3 PLL Control Register PLLCTLTable 5-7. PLL Control Register PLLCTL Field Descriptions PLL Controller Registers5.4.5 PLL Controller Divider 1 Register PLLDIV1 5.4.4 PLL Multiplier Control Register PLLMFigure 5-6. PLL Multiplier Control Register PLLM Table 5-8. PLL Multiplier Control Register PLLM Field Descriptions5.4.7 PLL Controller Divider 3 Register PLLDIV3 5.4.6 PLL Controller Divider 2 Register PLLDIV2Figure 5-8. PLL Controller Divider 2 Register PLLDIV2 Figure 5-9. PLL Controller Divider 3 Register PLLDIV3Figure 5-10. Oscillator Divider 1 Register OSCDIV1 5.4.8 Oscillator Divider 1 Register OSCDIV1Table 5-12. Oscillator Divider 1 Register OSCDIV1 Field Descriptions PLL Controller RegistersFigure 5-11. Bypass Divider Register BPDIV 5.4.9 Bypass Divider Register BPDIVTable 5-13. Bypass Divider Register BPDIV Field Descriptions PLL Controller RegistersFigure 5-12. PLL Controller Command Register PLLCMD 5.4.10 PLL Controller Command Register PLLCMDTable 5-14. PLL Controller Command Register PLLCMD Field Descriptions 5.4.11 PLL Controller Status Register PLLSTATFigure 5-14. PLL Controller Clock Align Control Register ALNCTL 5.4.12 PLL Controller Clock Align Control Register ALNCTLPLL Controller Registers FieldFigure 5-15. PLLDIV Ratio Change Status Register DCHANGE 5.4.13 PLLDIV Ratio Change Status Register DCHANGEPLL Controller Registers FieldFigure 5-16. Clock Enable Control Register CKEN 5.4.14 Clock Enable Control Register CKENTable 5-18. Clock Enable Control Register CKEN Field Descriptions PLL Controller RegistersFigure 5-17. Clock Status Register CKSTAT 5.4.15 Clock Status Register CKSTATTable 5-19. Clock Status Register CKSTAT Field Descriptions PLL Controller RegistersFigure 5-18. SYSCLK Status Register SYSTAT 5.4.16 SYSCLK Status Register SYSTATTable 5-20. SYSCLK Status Register SYSTAT Field Descriptions PLL Controller RegistersPower Domain and Module Topology Power and Sleep ControllerPower Domain and Module States Executing State Transitions6.1 Introduction Figure 6-1. Power and Sleep Controller PSC IntegrationTable 6-1. DM643x DMP Default Module Configuration 6.2 Power Domain and Module Topology6.3.1 Power Domain States 6.3 Power Domain and Module States6.3.2 Module States Table 6-2. Module States6.4.1 Power Domain State Transitions 6.3.3 Local Reset6.4 Executing State Transitions 6.4.2 Module State Transitions6.5 IcePick Emulation Support in the PSC Table 6-3. IcePick Emulation Commands6.6 PSC Interrupts 6.6.1 Interrupt Events6.6.1.1 Module State Emulation Events 6.6.1.2 Local Reset Emulation Events6.6.2 Interrupt Registers 6.7 PSC Registers Table 6-5. Power and Sleep Controller PSC Registers6.6.3 Interrupt Handling 6.7.2 Interrupt Evaluation Register INTEVAL 6.7.1 Peripheral Revision and Class Information Register PIDFigure 6-2. Peripheral Revision and Class Information Register PID Figure 6-3. Interrupt Evaluation Register INTEVAL6.7.4 Module Error Clear Register 1 MERRCR1 6.7.3 Module Error Pending Register 1 MERRPR1Figure 6-4. Module Error Pending Register 1 MERRPR1 Table 6-8. Module Error Pending Register 1 MERRPR1 Field Descriptions6.7.6 Power Domain Transition Status Register PTSTAT 6.7.5 Power Domain Transition Command Register PTCMDFigure 6-6. Power Domain Transition Command Register PTCMD Figure 6-7. Power Domain Transition Status Register PTSTATFigure 6-8. Power Domain Status 0 Register PDSTAT0 6.7.7 Power Domain Status 0 Register PDSTAT0Table 6-12. Power Domain Status 0 Register PDSTAT0 Field Descriptions Power and Sleep ControllerFigure 6-9. Power Domain Control 0 Register PDCTL0 6.7.8 Power Domain Control 0 Register PDCTL0Table 6-13. Power Domain Control 0 Register PDCTL0 Field Descriptions Power and Sleep Controller6.7.9 Module Status n Register MDSTATn Power and Sleep ControllerFigure 6-10. Module Status n Register MDSTATn Table 6-14. Module Status n Register MDSTATn Field Descriptions6.7.10 Module Control n Register MDCTLn Power and Sleep ControllerFigure 6-11. Module Control n Register MDCTLn Table 6-15. Module Control n Register MDCTLn Field DescriptionsSubmit Documentation Feedback Power and Sleep ControllerSPRU978E-March DSP Sleep Mode Management Power Management3.3 V I/O Power Down Video DAC Power Down7.2 PSC and PLLC Overview Table 7-1. Power Management Features7.1 Overview 7.3 Clock Management 7.3.3 PLL Bypass and Power Down7.3.1 Module Clock ON/OFF 7.3.2 Module Clock Frequency Scaling7.4.1 DSP Sleep Modes 7.4 DSP Sleep Mode Management7.4.2 DSP Module Clock ON/OFF 7.4.2.1 DSP Module Clock ON7.4.2.2 DSP Module Clock Off 7.5 3.3 V I/O Power Down7.6 Video DAC Power Down Submit Documentation Feedback Power ManagementSPRU978E-March Interrupt Controller Interrupt ControllerChapter Submit Documentation Feedback Interrupt ControllerSPRU978E-March 3.3 V I/O Power-Down Control Device ConfigurationBoot Control System Module9.3.2 Device Boot Configuration Status 9.3 Device Configuration9.1 Overview 9.2 Device Identification9.5.1 Timer Control 9.4 3.3 V I/O Power-Down Control9.5 Peripheral Status and Control 9.5.2 VPSS Clock and DAC ControlTable 9-1. TMS320DM643x DMP Master IDs 9.6 Bandwidth Management9.6.1 Bus Master DMA Priority Control Table 9-2. TMS320DM643x DMP Default Master Priorities 9.6.2 EDMA Transfer Controller Configuration9.7 Boot Control Submit Documentation Feedback System ModuleSPRU978E-March Reset Pins ResetDevice Configurations at Reset DSP Reset10.3 Device Configurations at Reset 10.2 Reset PinsTable 10-1. Reset Types 10.1 Overview10.4.1 DSP Local Reset 10.4 DSP Reset10.4.2 DSP Module Reset 10.4.2.1 Software Reset Disable SwRstDisable10.4.2.2 Synchronous Reset SyncReset Chapter Boot ModesSubmit Documentation Feedback Boot ModesSPRU978E-March Appendix A Revision HistoryTable A-1. Document Revision History SPRU978E-MarchIMPORTANT NOTICE power.ti.comProducts Applications