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PLL Controller Registers
5.4.1 Peripheral ID Register (PID)
The peripheral ID register (PID) is shown in Figure
Figure 5-3. Peripheral ID Register (PID)
31 | 24 | 23 | 16 |
Reserved |
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| TYPE |
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15 | 8 | 7 | 0 |
CLASS |
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| REV |
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LEGEND: R = Read only; |
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| Table |
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
TYPE |
| Peripheral type | |
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| 1h | PLLC |
CLASS |
| Peripheral class | |
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| 8h | Current class |
REV |
| Peripheral revision | |
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| Dh | Current revision |
5.4.2 Reset Type Status Register (RSTYPE)
The reset type status register (RSTYPE) is shown in Figure
Figure 5-4. Reset Type Status Register (RSTYPE)
31 |
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| 16 |
| Reserved |
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15 | 3 | 2 | 1 | 0 |
Reserved |
| MRST | XWRST | POR |
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LEGEND: R = Read only;
Table 5-6. Reset Type Status Register (RSTYPE) Field Descriptions
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
2 | MRST | Maximum reset. If 1, maximum reset was the reset to occur that is of highest priority. | |
1 | XWRST | External warm reset. If 1, warm reset (RESET) was the last reset to occur that is of highest priority. | |
0 | POR | Power on reset. If 1, power on reset (POR) was the last reset to occur that is of highest priority. |
PLL Controller | 49 | |
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