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Intel BX80633I74820K, BX80633I74930K 7.3 Power-On Configuration (POC) Options

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Datasheet 61

Electrical Specifications

Notes:

1. Refer to Chapter 6 for signal description details.

2. DDR{0/1/2/3} refers to DDR3 Channel 0, DDR3 Channel 1, DDR3 Channel 2 and DDR3 Channel 3.

Notes:

1. Refer to Table 7-17 for details on the RON (Buffer on Resistance) value for this signal.

7.3 Power-On Configuration (POC) Options

Several configuration options can be configured by hardware. The processor samples

its hardware configuration at reset, on the active-to-inactive transition of RESET_N, or

upon assertion of PWRGOOD (inactive-to-active transition). For specifics on these

options, refer to Table 7-7.

The sampled information configures the processor for subsequent operation. These

configuration options cannot be changed, except by another reset transition of the

latching signal (RESET_N or PWRGOOD).

Notes:

1. Output tri-state option enables Fault Resilient Booting (FRB). The RESET_N signal is used to latch

PROCHOT_N for enabling FRB mode.

2. BIST_ENABLE is sampled at RESET_N de-assertion (on the falling edge).

3. This signal is sampled after PWRGOOD assertion.

Power/Other Signals

Power / Ground VCC, VTTA, VTTD, VCCD_01, VCCD_23,VCCPLL, VSA and VSS

Sense Points

VCC_SENSE

VSS_VCC_SENSE

VSS_VTTD_SENSE

VTTD_SENSE

VSA_SENSE

VSS_VSA_SENSE

Table 7-5. Signal Groups (Sheet 3 of 3)

Differential /

Single Ended Buffer Type Signals1

Table 7-6. Signals with On-Die Termination

Signal Name Pull-Up /

Pull-Down Rail Value Units Notes

DDR{0/1}_PAR_ERR_N Pull-Up VCCD_01 65 

DDR{2/3}_PAR_ERR_N Pul-Up VCCD_23 65 

TXT_AGENT Pull-Down VSS 2K 

SAFE_MODE_BOOT Pull-Down VSS 2K 

BIST_ENABLE Pul-Up VTT 2K 

TXT_PLTEN Pul-Up VTT 2K 

EAR_N Pull-Up VTT 2K 1

Table 7-7. Power-On Configuration Option Lands

Configuration Option Land Name Notes

Output tri state PROCHOT_N 1

Execute BIST (Built-In Self Test) BIST_ENABLE 2

Enable Intel® Trusted Execution Technology (Intel® TXT) Platform TXT_PLTEN 3

Power-up Sequence Halt for ITP configuration EAR_N 3

Enable Intel Trusted Execution Technology (Intel TXT) Agent TXT_AGENT 3

Enable Safe Mode Boot SAFE_MODE_BOOT 3

Contents

Main Page Table of Contents Page Figures Tables Page Page 1 1.1 Processor Feature Details 1.2 Supported Technologies 1.3 Interfaces 1.3.1 System Memory Support 1.3.2 PCI Express* 1.3.3 Direct Media Interface Gen 2 (DMI2) 1.3.4 Platform Environment Control Interface (PECI) 1.4 Power Management Support 1.4.1 Processor Package and Core States 1.4.2 System States Support 1.4.3 Memory Controller 1.4.4 PCI Express* 1.6 Package Summary 1.7 Terminology Table 1-1. Terminology (Sheet 1 of 3) Table 1-1. Terminology (Sheet 2 of 3) 1.8 Related Documents Refer to the following documents for additional information. UI n = t n t Table 1-1. Terminology (Sheet 3 of 3) Table 1-2. Processor Documents Table 1-3. Public Specifications 2 2.1 System Memory Interface 2.1.1 System Memory Technology Support 2.1.2 System Memory Timing Support 2.2 PCI Express* Interface 2.2.1 PCI Express* Architecture 2.2.1.1 Transaction Layer 2.2.1.2 Data Link Layer 2.2.1.3 Physical Layer 2.2.2 PCI Express* Configuration Mechanism 2.3 Direct Media Interface 2 (DMI2) / PCI Express* Interface 2.3.1 DMI2 Error Flow 2.3.2 Processor / PCH Compatibility Assumptions 2.3.3 DMI2 Link Down 2.4 Platform Environment Control Interface (PECI) 3 3.1 Intel Virtualization Technology (Intel VT) 3.1.1 Intel VT-x Objectives 3.1.2 Intel VT-x Features 3.1.3 Intel VT-d Objectives 3.1.3.1 Intel VT-d Features Supported 3.1.4 Intel Virtualization Technology Processor Extensions 3.2 Security Technologies 3.2.1 Intel Advanced Encryption Standard New Instructions (Intel AES-NI) Instructions 3.2.2 Execute Disable Bit 3.3 Intel Hyper-Threading Technology (Intel HT Technology) 3.4 Intel Turbo Boost Technology 3.4.1 Intel Turbo Boost Operating Frequency 3.5 Enhanced Intel SpeedStep Technology 3.6 Intel Advanced Vector Extensions (Intel AVX) Page 4 4.1 Advanced Configuration and Power Interface (ACPI) States Supported 4.1.1 System States 4.1.2 Processor Package and Core States Table 4-2. Package C-State Support Table 4-3. Core C-State Support 4.1.3 Integrated Memory Controller (IMC) States 4.1.4 Direct Media Interface Gen 2 (DMI2) / PCI Express* Link States Table 4-4. System Memory Power States Table 4-5. DMI2 / PCI Express* Link States 4.1.5 G, S, and C State Combinations 4.2 Processor Core / Package Power Management 4.2.1 Enhanced Intel SpeedStep Technology 4.2.2 Low-Power Idle States 4.2.3 Requesting Low-Power Idle States 4.2.4 Core C-states 4.2.4.1 Core C0 State 4.2.4.2 Core C1/C1E State 4.2.4.3 Core C3 State 4.2.4.4 Core C6 State 4.2.5 Package C-States 4.2.5.1 Package C0 State 4.2.5.2 Package C1/C1E State 4.2.5.3 Package C2 State 4.2.5.4 Package C3 State 4.2.5.5 Package C6 State 4.2.6 Package C-State Power Specifications 4.3 System Memory Power Management 4.3.1 CKE Power-Down 4.3.2 Self-Refresh 4.3.2.1 Self-Refresh Entry 4.3.2.2 Self-Refresh Exit 4.3.2.3 DLL and PLL Shutdown 4.4 Direct Media Interface 2 (DMI2) / PCI Express* Power Management 5 Specifications 6 6.1 System Memory Interface Signals Table 6-1. Memory Channel DDR0, DDR1, DDR2, DDR3 6.2 PCI Express* Based Interface Signals Note: PCI Express* Ports 1, 2, and 3 signals are receive and transmit differential pairs. Table 6-2. Memory Channel Miscellaneous Table 6-3. PCI Express* Port 1 Signals Table 6-4. PCI Express* Port 2 Signals (Sheet 1 of 2) Table 6-5. PCI Express* Port 3 Signals Table 6-6. PCI Express* Miscellaneous Signals Table 6-4. PCI Express* Port 2 Signals (Sheet 2 of 2) 6.3 Direct Media Interface Gen 2 (DMI2) / PCI Express* Port 0 Signals 6.4 Platform Environment Control Interface (PECI) Signal Table 6-7. DMI2 and PCI Express Port 0 Signals Table 6-8. Platform Environment Control Interface (PECI) Signals Table 6-9. System Reference Clock (BCLK{0/1}) Signals 6.7 Serial Voltage Identification (SVID) Signals 6.8 Processor Asynchronous Sideband and Miscellaneous Signals Table 6-11. Serial Voltage Identification (SVID) Signals Table 6-12. Processor Asynchronous Sideband Signals (Sheet 1 of 3) Table 6-10. Joint Test Action Group (JTAG) and Test Access Port (TAP) Signals (Sheet 2 of 2) Table 6-12. Processor Asynchronous Sideband Signals (Sheet 2 of 3) Table 6-13. Miscellaneous Signals Table 6-12. Processor Asynchronous Sideband Signals (Sheet 3 of 3) 6.9 Processor Power and Ground Supplies Table 6-14. Power and Ground Signals 7 7.1 Processor Signaling 7.1.1 System Memory Interface Signal Groups 7.1.2 PCI Express* Signals 7.1.3 Direct Media Interface Gen 2 (DMI2) / PCI Express* Signals 7.1.4 Platform Environmental Control Interface (PECI) 7.1.4.1 Input Device Hysteresis 7.1.5 System Reference Clocks (BCLK{0/1}_DP, BCLK{0/1}_DN) 7.1.5.1 PLL Power Supply 7.1.6 Joint Test Action Group (JTAG) and Test Access Port (TAP) Signals 7.1.7 Processor Sideband Signals 7.1.8 Power, Ground and Sense Signals 7.1.8.1 Power and Ground Lands 7.1.8.2 Decoupling Guidelines 7.1.8.3 Voltage Identification (VID) Page Page Table 7-2. Serial Voltage Identification (SVID) Address Usage Table 7-3. VR12.0 Reference Code Voltage Identification (VID) Table (Sheet 1 of 2) 7.1.9 Reserved or Unused Signals 7.2 Signal Group Summary Table 7-3. VR12.0 Reference Code Voltage Identification (VID) Table (Sheet 2 of 2) Table 7-4. Signal Description Buffer Types Table 7-5. Signal Groups (Sheet 1 of 3) Table 7-5. Signal Groups (Sheet 2 of 3) 7.3 Power-On Configuration (POC) Options Table 7-5. Signal Groups (Sheet 3 of 3) Table 7-6. Signals with On-Die Termination Table 7-7. Power-On Configuration Option Lands 7.4 Absolute Maximum and Minimum Ratings 7.4.1 Storage Conditions Specifications 7.5 DC Specifications 7.5.1 Voltage and Current Specifications Table 7-9. Storage Condition Ratings (Sheet 2 of 2) Table 7-10. Voltage Specifications (Sheet 1 of 2) Table 7-10. Voltage Specifications (Sheet 2 of 2) Table 7-11. Current Specifications 7.5.2 Die Voltage Validation 7.5.2.1 VCC Overshoot Specifications 7.5.3 Signal DC Specifications Table 7-14. PECI DC Specifications Table 7-13. DDR3 and DDR3L Signal DC Specifications (Sheet 2 of 2) Table 7-15. System Reference Clock (BCLK{0/1}) DC Specifications Table 7-16. SMBus DC Specifications Table 7-17. Joint Test Action Group (JTAG) and Test Access Point (TAP) Signals DC Specifications Table 7-18. Serial VID Interface (SVID) DC Specifications Table 7-19. Processor Asynchronous Sideband DC Specifications Table 7-20. Miscellaneous Signals DC Specifications 7.5.3.1 PCI Express* DC Specifications 7.5.3.2 DMI2/PCI Express* DC Specifications 7.5.3.3 Reset and Miscellaneous Signal DC Specifications Page Table 8-1. Land List by Land Name (Sheet 1 of 42) Table 8-1. Land List by Land Name (Sheet 2 of 42) Table 8-1. Land List by Land Name (Sheet 3 of 42) Table 8-1. Land List by Land Name (Sheet 4 of 42) Table 8-1. Land List by Land Name (Sheet 5 of 42) Table 8-1. Land List by Land Name (Sheet 6 of 42) Table 8-1. Land List by Land Name (Sheet 7 of 42) Table 8-1. Land List by Land Name (Sheet 8 of 42) Table 8-1. Land List by Land Name (Sheet 9 of 42) Table 8-1. Land List by Land Name (Sheet 10 of 42) Table 8-1. Land List by Land Name (Sheet 11 of 42) Table 8-1. Land List by Land Name (Sheet 12 of 42) Table 8-1. Land List by Land Name (Sheet 13 of 42) Table 8-1. Land List by Land Name (Sheet 14 of 42) Table 8-1. Land List by Land Name (Sheet 15 of 42) Table 8-1. Land List by Land Name (Sheet 16 of 42) Table 8-1. Land List by Land Name (Sheet 17 of 42) Table 8-1. Land List by Land Name (Sheet 18 of 42) Table 8-1. Land List by Land Name (Sheet 19 of 42) Table 8-1. Land List by Land Name (Sheet 20 of 42) Table 8-1. Land List by Land Name (Sheet 21 of 42) Table 8-1. Land List by Land Name (Sheet 22 of 42) Table 8-1. Land List by Land Name (Sheet 23 of 42) Table 8-1. Land List by Land Name (Sheet 24 of 42) Table 8-1. Land List by Land Name (Sheet 25 of 42) Table 8-1. Land List by Land Name (Sheet 26 of 42) Table 8-1. Land List by Land Name (Sheet 27 of 42) Table 8-1. Land List by Land Name (Sheet 28 of 42) Table 8-1. Land List by Land Name (Sheet 29 of 42) Table 8-1. Land List by Land Name (Sheet 30 of 42) Table 8-1. Land List by Land Name (Sheet 31 of 42) Table 8-1. Land List by Land Name (Sheet 32 of 42) Table 8-1. Land List by Land Name (Sheet 33 of 42) Table 8-1. Land List by Land Name (Sheet 34 of 42) Table 8-1. Land List by Land Name (Sheet 35 of 42) Table 8-1. Land List by Land Name (Sheet 36 of 42) Table 8-1. Land List by Land Name (Sheet 37 of 42) Table 8-1. Land List by Land Name (Sheet 38 of 42) Table 8-1. Land List by Land Name (Sheet 39 of 42) Table 8-1. Land List by Land Name (Sheet 40 of 42) Table 8-1. Land List by Land Name (Sheet 41 of 42) Table 8-1. Land List by Land Name (Sheet 42 of 42) Table 8-2. Land List by Land Number (Sheet 1 of 42) Table 8-2. Land List by Land Number (Sheet 2 of 42) Table 8-2. Land List by Land Number (Sheet 3 of 42) Table 8-2. Land List by Land Number (Sheet 4 of 42) Table 8-2. Land List by Land Number (Sheet 5 of 42) Table 8-2. Land List by Land Number (Sheet 6 of 42) Table 8-2. Land List by Land Number (Sheet 7 of 42) Table 8-2. Land List by Land Number (Sheet 8 of 42) Table 8-2. Land List by Land Number (Sheet 9 of 42) Table 8-2. Land List by Land Number (Sheet 10 of Table 8-2. Land List by Land Number (Sheet 11 of Table 8-2. Land List by Land Number (Sheet 12 of Table 8-2. Land List by Land Number (Sheet 13 of Table 8-2. Land List by Land Number (Sheet 14 of Table 8-2. Land List by Land Number (Sheet 15 of Table 8-2. Land List by Land Number (Sheet 16 of Table 8-2. Land List by Land Number (Sheet 17 of Table 8-2. Land List by Land Number (Sheet 18 of Table 8-2. Land List by Land Number (Sheet 19 of Table 8-2. Land List by Land Number (Sheet 20 of Table 8-2. Land List by Land Number (Sheet 21 of Table 8-2. Land List by Land Number (Sheet 22 of Table 8-2. Land List by Land Number (Sheet 23 of Table 8-2. Land List by Land Number (Sheet 24 of Table 8-2. Land List by Land Number (Sheet 25 of Table 8-2. Land List by Land Number (Sheet 26 of Table 8-2. Land List by Land Number (Sheet 27 of Table 8-2. Land List by Land Number (Sheet 28 of Table 8-2. Land List by Land Number (Sheet 29 of Table 8-2. Land List by Land Number (Sheet 30 of Table 8-2. Land List by Land Number (Sheet 31 of Table 8-2. Land List by Land Number (Sheet 32 of Table 8-2. Land List by Land Number (Sheet 33 of Table 8-2. Land List by Land Number (Sheet 34 of Table 8-2. Land List by Land Number (Sheet 35 of Table 8-2. Land List by Land Number (Sheet 36 of Table 8-2. Land List by Land Number (Sheet 37 of Table 8-2. Land List by Land Number (Sheet 38 of Table 8-2. Land List by Land Number (Sheet 39 of Table 8-2. Land List by Land Number (Sheet 40 of Table 8-2. Land List by Land Number (Sheet 41 of Table 8-2. Land List by Land Number (Sheet 42 of 9 10 10.1 Introduction 10.2 Boxed Processor Contents