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Intel Q35 Express, Core 2 Duo Revision History, Date, Description, Initial release, October

Models: Q35 Express Core 2 Duo

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Revision History—Intel Core 2 Duo Processor and Intel Q35 Express Chipset

Revision History

Date	Revision	Description

October 2007	001	Initial release

	Intel® CoreTM 2 Duo Processor and Intel ® Q35 Express Chipset Development Kit
October 2007	User’s Manual
Order Number: 318476-001US	5

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Intel Q35 Express, Core 2 Duo user manual Revision History, Date, Description, Initial release, October

Contents

Intel CoreTM 2 Duo Processor and Intel Q35 Express Chipset User’s ManualDevelopment Kit OctoberOctober User’s ManualFigures ContentsIntel Core 2 Duo Processor and Intel Q35 Express Chipset-Contents TablesDate Revision HistoryRevision DescriptionChapter 2.0, “Development Kit Hardware Features” 1.1 Content OverviewChapter 3.0, “Setting Up and Configuring the Development Kit” 1.0 About This ManualSheet 1 of 1.3 Glossary of Terms and AcronymsDefinition 1.5 Product Literature 1.4 Support Options1.4.1 Electronic Support Systems 1.4.2 Additional Technical SupportIntel Literature Centers 2.1 Intel Q35 Express Chipset Development Kit Overview 2.0 Development Kit Hardware FeaturesBoard Features 2.2 System Block DiagramTable 3. Development Kit Hardware Items 2.3 Development Kit Inventory ChecklistsFigure 2. Intel Q35 Express Chipset Development Kit block diagram Internal I/O headers Table 4. Development Kit Board SpecificationSupported Intel Technologies Sheet 1 of Features/support2.4 Processor Support Table 7. Additional Features2.5 System Memory Supported Intel Technologies Sheet 2 ofFigure 3. Memory Channel and DIMM Configuration 2.5.1 Dual Channel Interleaved Mode ConfigurationsFigure 5. Dual Channel Interleaved Mode Configuration with 3x DIMMs Figure 4. Dual Channel Interleaved Mode Configuration with 2x DIMMsFigure 7. Single Channel Asymmetric Mode Configuration with 1x DIMM 2.5.2 Single Channel Asymmetric Mode ConfigurationsFigure 6. Dual Channel Interleaved Mode Configuration with 4x DIMMs 2.6.1 Audio-Connectors 2.6 Back-Panel ConnectorsFigure 8. Single Channel Asymmetric Mode Configuration with 3x DIMMs Figure 9. Back-panel Connectors2.6.4 Coaxial S/PDIF In/Out Connector 2.6.2 RJ-45 LAN Connector with Integrated LEDsFigure 10. LAN Connector LED locations LAN Connector LED status2.7.2 Power LEDs 2.7 Debug FeaturesFigure 11. ITP-XDP Connector location J2BC 2.7.1 Extended Debug Probe XDP2.7.4 Voltage Reference 2.8 Development Kit Major Connectors and JumpersVoltage Reference detail Figure 12. Major Jumper and Header Locations2.8.2 USB 2.0 Front Panel 2.8.1 Jumper Functions2.8.3 1394a Header Table 11. USB Front PanelFigure 13. Location for 1394a Header and USB Front Panel 2.9 SPI Removal / Installation TechniqueTable 12. 1394a Header Pin NumberFigure 14. SPI Socket with Retaining Clip 2.9.2 SPI Device Installation2.9.1 SPI Device Removal 2. Close the cover Figure 15. SPI Device Installation1. Place the fresh IC into the socket. Match pin 1. on the IC3.2 Installing Board Standoffs 3.0 Setting Up and Configuring the Development Kit3.1 Overview Figure 16. Intel Q35 Development KitsFigure 17. Mounting Hole Locations 3.3.1 SRM Alignment on any BTX Board 3.3 BTX Heatsink Setup with SRMFigure 18. Mounting the Standoff for BTX Heatsink Figure 19. Casing with “Support and Retention Module”Figure 21. Heatsink Alignment Figure 20. BTX board alignment on SRMFigure 22. Tightening Heatsink on the SRM and Board 3.4 Board Setup and Configuration before BootFigure 23. CPU Fan location 3.5 Post Codes Definitions Figure 24. 2x12 Standard power supply and 2x2 power supply3.5.1 Normal Post Codes Uncompressed INIT code checkpointsRuntime POST Code Checkpoints Boot Block Recovery Code CheckpointsOEM memory detection/configuration error. Range reserved for Set up floppy controller and data. Attempt to read from floppyof KB and MS Prepare runtime image for different BIOS modules. Initialize MS Order Number 318476001US User’s ManualOctober

Revision History

Date

Revision

Description

October 2007

Initial release