Intel Q35 Express, Core 2 Duo Boot Block Recovery Code Checkpoints, Runtime POST Code Checkpoints

Setting Up and Configuring the Development Kit—Intel Core 2 Duo Processor and Intel Q35 Express Chipset

D7	Restore CPUID value to register. Bootblock runtime module
	transferred to system memory.
D8	Main BIOS runtime code is to be decompressed.
D9	Copy main BIOS into system memory.
E1-E8	OEM memory detection/configuration error. Range reserved for
	chipset vendors/OEMs.
EC-EE
Boot Block Recovery Code Checkpoints
E0	Initialize Floppy Controller, DMA controller and interrupt
	controller.
E9	Set up floppy controller and data. Attempt to read from floppy.
EA	Enable ATAPI hardware. Attempt to read from ARMD and ATAPI
	CDROM.
EB	Disable ATAPI hardware. Jump back to checkpoint E9.
EF	Read error occurred on media. Jump back to checkpoint EB.
EF	Floppy read error.
F0	Search for pre-defined recovery file in root directory.
F1	Recovery file not found.
F2	Start reading FAT table and analyze FAT to find the clusters
	occupied by the recovery file.
F3	Start reading recovery file cluster by cluster.
F5	Disable L1 cache.
FA	Check validity of recovery file configuration against
	configuration of FLASH part.
FB	Enable FLASH write through POEM and chipset specific method.
	Detect FLASH type.
F4	Recovery file size does not match FLASH part size.
FC	Erase FLASH.
FD	Program FLASH.
FF	Flash program successful. Disable FLASH write. Restore CPUID
	into register.
Runtime POST Code Checkpoints
03	Disable NMI, Parity, EGA video and DMA controllers. Initialize
	BIOS, POST and runtime data area.
04	Verify CMOS checksum. Initialize status register A.
05	Initialize interrupt hardware and interrupt vector table.
06	Do R/W to CH-2 count reg. Initialize CH-0 as system timer.
	Install POSTINTCH handler.
	Enable IRQ0 in PIC for system timer interrupt.

	Intel® CoreTM 2 Duo Processor and Intel ® Q35 Express Chipset Development Kit
October 2007	User’s Manual
Order Number: 318476001US	33